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sja1000: synchronous with AXI, duplex register access (WIP)
[fpga/zynq/canbench-sw.git] / system / ip / sja1000_1.0 / hdl / can_register_asyn_syn.v
2016-05-12 Martin Jerabekadded sja1000 IP blob | commitdiff | raw
CAN benchmark FPGA design and software for MicroZed board