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microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
[fpga/zynq/canbench-sw.git] / system / ip / audio_single_pwm_1.0 / hdl / pulse_gen.vhdl
1 --
2 -- * pulse generator *
3 --
4 -- based on code from LXPWR motion control board (c) PiKRON Ltd
5 -- idea by Pavel Pisa PiKRON Ltd <ppisa@pikron.com>
6 --
7 -- license: BSD
8 --
9
10 library ieee;
11 use ieee.std_logic_1164.all;
12 use ieee.numeric_std.all;
13
14 entity pulse_gen is
15         generic (
16                 duration_width_g : natural := 4
17         );
18         port
19         (
20                 clk_i      : in std_logic;                              --clk to divide
21                 en_i       : in std_logic;                              --enable bit?
22                 reset_i    : in std_logic;                              --asynch. reset
23                 trigger_i  : in std_logic;                              --start to generate pulse
24                 duration_i : in std_logic_vector(duration_width_g-1 downto 0);--duration/interval of the pulse
25                 q_out_o    : out std_logic                              --generates pulse for given duration
26         );
27 end pulse_gen;
28
29 architecture behavioral of pulse_gen is
30         signal cnt_val_s : natural range 0 to (2**duration_width_g - 1);        --counter value before DFF
31         signal cnt_val_r : natural range 0 to (2**duration_width_g - 1);        --counter value after DFF
32 begin
33
34 comb: process (reset_i, en_i, duration_i, trigger_i, cnt_val_r)
35         begin
36                 if reset_i = '1' then --reset detection
37                         cnt_val_s <= 0;         --set defined value
38                         q_out_o   <= '0';                               --reset output
39                 else
40                         if en_i = '0' then                              --stop-state
41                                 cnt_val_s <= cnt_val_r;                 --hold the value
42                         else
43                                 if trigger_i = '1' then                 --trigger pulse generator
44                                         if to_integer(unsigned(duration_i)) = 0 then
45                                                 q_out_o   <= '0';
46                                         else
47                                                 q_out_o   <= '1';
48                                         end if;
49                                         cnt_val_s <= to_integer(unsigned(duration_i)); --set initial value
50                                 elsif cnt_val_r = 0 then                        --pulse finished
51                                         cnt_val_s <= cnt_val_r;
52                                         q_out_o   <= '0';               --set output
53                                 else
54                                         cnt_val_s <= cnt_val_r - 1;     --decrement counter
55                                         q_out_o   <= '1';               --reset output
56                                 end if;
57                         end if;
58                 end if;
59         end process;
60
61 seq: process
62         begin
63                 wait until clk_i'event and clk_i = '1';
64                 cnt_val_r <= cnt_val_s;
65         end process;
66
67 end behavioral;
68