1 #==============================================================================#
3 #==============================================================================#
5 NET "CLK_24MHz" LOC = "A11" | PERIOD = 41.7 ns LOW 20.9 ns;
7 NET "RESET" LOC = "B6";
10 #==============================================================================#
12 #==============================================================================#
14 NET "TXD" LOC = "A7"; # output from the board (from FPGA)
15 NET "RXD" LOC = "B7"; # input to the board (to FPGA)
17 #==============================================================================#
18 # Incremental rotary encoder #
19 #==============================================================================#
20 # Connected to the header J4.
22 NET "ROT_FEED" LOC = "H2"; # pin 01
23 NET "ROT_A" LOC = "J2" | PULLDOWN; # pin 03
24 NET "ROT_B" LOC = "K2" | PULLDOWN; # pin 05
25 NET "ROT_PRESS" LOC = "E4" | PULLDOWN; # pin 07
27 #==============================================================================#
29 #==============================================================================#
30 # Connected to the header J7 (LVDS TX STATUS).
32 NET "PWM" LOC = "C1"; # pin 01