From: Vladimir Burian <buriavl2@fel.cvut.cz>
Date: Fri, 27 May 2011 06:11:04 +0000 (+0200)
Subject: Keeping hierarchy during hardware synthesis.
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/virtex2/msp_motion.git/commitdiff_plain/bb6b940d288b29282f2429b4cdb9c92effd7ac94

Keeping hierarchy during hardware synthesis.

Does not propagate to place & route stage, so optimization is still
working. But we can see in  floorplan which part of FPGA implements
which entity.
---

diff --git a/build/Makefile b/build/Makefile
index 6eb12ff..fa08461 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -105,6 +105,7 @@ re-synthesize $(NGC): $(addrefix $(SRC)/,$(PRJ))
 	  -top $(TOP) \
 	  -p $(DEVICE) \
 	  -opt_mode Speed \
+          -keep_hierarchy soft \
 	  -opt_level 1" | xst | tee xst.log