+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+--------------------------------------------------------------------------------
+
+entity event_rwc is
+ generic (
+ W : integer := 16); -- Event port width (pin count)
+ port (
+ -- Peripheral bus interface
+ ACK_O : out std_logic;
+ CLK_I : in std_logic;
+ DAT_I : in std_logic_vector (W-1 downto 0);
+ DAT_O : out std_logic_vector (W-1 downto 0);
+ RST_I : in std_logic;
+ SEL_I : in std_logic;
+ STB_I : in std_logic;
+ WE_I : in std_logic;
+ -- Event port pins
+ EVENT_I : in std_logic_vector (W-1 downto 0);
+ EVENT_O : out std_logic_vector (W-1 downto 0));
+end event_rwc;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of event_rwc is
+
+ signal status : std_logic_vector (W-1 downto 0) := (others => '0');
+ signal write_en : std_logic;
+
+begin
+
+ ACK_O <= SEL_I and STB_I;
+ DAT_O <= status;
+
+ EVENT_O <= status;
+
+ write_en <= SEL_I and STB_I and WE_I;
+
+ process (CLK_I, RST_I) is
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ status <= (others => '0');
+ else
+ if write_en = '1' then
+ status <= (status and not DAT_I) or EVENT_I;
+ else
+ status <= status or EVENT_I;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end behavioral;
+