architecture rtl of msp_motion is
+ signal reset_p : std_logic;
+
------------------------------------------------------------------------------
-- OpenMSP430 softcore MCU module
------------------------------------------------------------------------------
signal per_en : std_logic;
signal per_addr : std_logic_vector (7 downto 0);
-- Interrupt
+ --signal irq : std_logic_vector (13 downto 0) := (others => '0');
signal irq : std_logic_vector (13 downto 0);
signal irq_acc : std_logic_vector (13 downto 0);
signal DPA_SEL : std_logic;
signal DPA_STB : std_logic;
-- Auxiliary register used to generate IRF_ACK
- signal IRF_ACK_REG : std_logic;
+ signal IRF_ACK_REG : std_logic := '0';
-- Auxiliary signal used to form B-port address
signal DPB_ADR : std_logic_vector (9 downto 0);
port map (
dco_clk => CLK_24MHz,
lfxt_clk => '0',
- reset_n => RESET,
+ reset_n => '1',
rxd => RXD,
txd => TXD,
per_addr => per_addr,
aclk_en => open,
smclk_en => open,
mclk => mclk,
- puc => puc,
+ puc => open,
dmem_addr => dmem_addr,
dmem_ce => dmem_ce,
dmem_we => dmem_we,
dmem_din => dmem_din,
dmem_dout => dmem_dout);
+ puc <= '0';
+ reset_p <= not RESET;
+
+ STARTUP_VIRTEX2_inst : STARTUP_VIRTEX2
+ port map (
+ CLK => open,
+ -- Clock input for start-up sequence
+ GSR => reset_p, -- Global Set/Reset input (GSR cannot be used for the port name)
+ GTS => open); -- Global 3-state input (GTS cannot be used for the port name)
+
+
-- External data bus address decoder and data multiplexer.
------------------------------------------------------------------------------
-- When connection more memories, be aware that 'dmem_dout' can vary only when
------------------------------------------------------------------------------
irq (13 downto 1) <= (others => '0');
- motor_irq_ff : process (mclk, puc) is
+ motor_irq_gen : process (mclk, puc) is
begin
if rising_edge (mclk) then
if puc = '1' or irq_acc (0) = '1' then
-- Motor feedback IRQ generator
-- f_motor_irq approx. 1 kHz
- mcc_irq_counter_1 : entity work.counter
+ irq_counter_1 : entity work.counter
generic map (
WIDTH => 5,
MAX => 22)
-- Motion Control Chain
------------------------------------------------------------------------------
mcc_exec_1 : entity work.mcc_exec
+ generic map (
+ AXIS_CNT => 1,
+ AXIS_CNT_W => 1)
port map (
CLK_I => mclk,
RST_I => puc,
+ MCC_AXIS_O => open,
+ MCC_DONE_O => open,
MCC_EN_I => '1',
MCC_EXEC_I => PWM_OW,
MCC_ERR_O => open,
------------------------------------------------------------------------------
-- PWM counter is shared by all PWM generators. Generator contains only
-- comparator and desired value.
- counter_1 : entity work.counter
+ pwm_counter : entity work.counter
generic map (
WIDTH => PWM_W,
MAX => 2**PWM_W - 2)
clk => mclk,
reset => puc,
din => PWM_DAT,
+ sel => '1',
we => PWM1_STB,
pwm_cnt => PWM_CNT,
pwm_cyc => PWM_OW,
clk => mclk,
reset => puc,
din => PWM_DAT,
+ sel => '1',
we => PWM2_STB,
pwm_cnt => PWM_CNT,
pwm_cyc => PWM_OW,
clk => mclk,
reset => puc,
din => PWM_DAT,
+ sel => '1',
we => PWM3_STB,
pwm_cnt => PWM_CNT,
pwm_cyc => PWM_OW,
pwm => PWM3_OUT);
-- PWM signals mapped to FPGA outputs, EN forced to '1'
- PWM0 <= PWM1_OUT;
+ PWM0 <= not PWM1_OUT;
PWM0_EN <= '1';
- PWM1 <= PWM2_OUT;
+ PWM1 <= not PWM2_OUT;
PWM1_EN <= '1';
- PWM2 <= PWM3_OUT;
+ PWM2 <= not PWM3_OUT;
PWM2_EN <= '1';
+
-- PWM is signalized on LEDs
LED0 <= PWM1_OUT;
LED1 <= PWM2_OUT;