--- /dev/null
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_arith.ALL;
+
+--------------------------------------------------------------------------------
+
+entity capture_reg is
+ generic (
+ W : integer := 32);
+ port (
+ -- Peripheral bus interface
+ ACK_O : out std_logic;
+ CLK_I : in std_logic;
+ DAT_O : out std_logic_vector (W-1 downto 0);
+ SEL_I : in std_logic;
+ STB_I : in std_logic;
+ -- QCounter component interface
+ EVENT_I : in std_logic;
+ CAPTURE_I : in std_logic_vector (W-1 downto 0));
+end capture_reg;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of capture_reg is
+
+ signal capture_mem : std_logic_vector (W-1 downto 0);
+
+--------------------------------------------------------------------------------
+
+begin
+
+ ACK_O <= SEL_I and STB_I;
+ DAT_O <= capture_mem;
+
+
+ process (CLK_I)
+ begin
+ if rising_edge(CLK_I) and EVENT_I = '1' then
+ capture_mem <= CAPTURE_I;
+ end if;
+ end process;
+
+end behavioral;
+