X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/virtex2/msp_motion.git/blobdiff_plain/b579a7181cd10cc36d4116fffb36075455758fc5..98ced3a20155c627d0c0f911fefa4536b5bbaea2:/mcu_periph/capture_reg.vhd

diff --git a/mcu_periph/capture_reg.vhd b/mcu_periph/capture_reg.vhd
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+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_arith.ALL;
+
+--------------------------------------------------------------------------------
+
+entity capture_reg is
+  generic (
+    W : integer := 32);
+  port (
+    -- Peripheral bus interface
+    ACK_O  : out std_logic;
+    CLK_I  : in  std_logic;
+    DAT_O  : out std_logic_vector (W-1 downto 0);
+    SEL_I  : in  std_logic;
+    STB_I  : in  std_logic;
+    -- QCounter component interface
+	EVENT_I   : in  std_logic;
+    CAPTURE_I : in  std_logic_vector (W-1 downto 0));
+end capture_reg;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of capture_reg is
+
+  signal capture_mem : std_logic_vector (W-1 downto 0);
+  
+--------------------------------------------------------------------------------
+
+begin
+
+  ACK_O <= SEL_I and STB_I;
+  DAT_O <= capture_mem;
+
+
+  process (CLK_I)
+  begin
+    if rising_edge(CLK_I) and EVENT_I = '1' then
+      capture_mem <= CAPTURE_I;
+    end if;
+  end process;
+
+end behavioral;
+