2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
7 use unisim.vcomponents.all;
9 --------------------------------------------------------------------------------
14 CLK_24MHz : in std_logic;
25 PWM0_EN : out std_logic;
27 PWM1_EN : out std_logic;
29 PWM2_EN : out std_logic;
31 IRC_INDEX : in std_logic;
40 --------------------------------------------------------------------------------
42 architecture rtl of msp_motion is
44 signal reset_p : std_logic;
46 ------------------------------------------------------------------------------
47 -- OpenMSP430 softcore MCU module
48 ------------------------------------------------------------------------------
49 signal mclk : std_logic;
50 signal puc : std_logic;
52 signal dmem_addr : std_logic_vector (11 downto 0);
53 signal dmem_ce : std_logic;
54 signal dmem_we : std_logic;
55 signal dmem_din : std_logic_vector (15 downto 0);
56 signal dmem_dout : std_logic_vector (15 downto 0);
58 signal per_din : std_logic_vector (15 downto 0);
59 signal per_dout : std_logic_Vector (15 downto 0);
60 signal per_wen : std_logic_vector (1 downto 0);
61 signal per_wen16 : std_logic;
62 signal per_en : std_logic;
63 signal per_addr : std_logic_vector (7 downto 0);
65 --signal irq : std_logic_vector (13 downto 0) := (others => '0');
66 signal irq : std_logic_vector (13 downto 0);
67 signal irq_acc : std_logic_vector (13 downto 0);
69 ------------------------------------------------------------------------------
71 ------------------------------------------------------------------------------
73 signal GPIO_IN : std_logic_vector (15 downto 0);
74 signal GPIO_OUT : std_logic_vector (15 downto 0);
75 signal GPIO_DAT_O : std_logic_vector (15 downto 0);
76 signal GPIO_SEL : std_logic;
77 -- Qcounter MCU interface
78 signal QCNT_DAT_O : std_logic_vector (15 downto 0);
79 signal QCNT_SEL : std_logic;
80 -- Motor feedback IRQ generator
81 signal MOTOR_IRQ : std_logic;
83 ------------------------------------------------------------------------------
84 -- Dual-port shared memory
85 ------------------------------------------------------------------------------
86 -- These signals of A-port (MCU) enables creation of external data encoder and
87 -- multiplexer in a case of multiple devices connected to the external data
88 -- bus. Otherwise useless.
89 signal DPA_DAT_O : std_logic_vector (15 downto 0);
90 signal DPA_SEL : std_logic;
91 signal DPA_STB : std_logic;
92 -- Auxiliary register used to generate IRF_ACK
93 signal IRF_ACK_REG : std_logic := '0';
94 -- Auxiliary signal used to form B-port address
95 signal DPB_ADR : std_logic_vector (9 downto 0);
97 ------------------------------------------------------------------------------
98 -- Motion Control Chain
99 ------------------------------------------------------------------------------
101 constant PWM_W : integer := 10;
102 constant LUT_ADR_W : integer := 11;
103 constant LUT_INIT : string := "sin1000.lut";
105 -- Bus interface to the shared memory
106 signal IRF_ACK : std_logic;
107 signal IRF_ADR : std_logic_vector (4 downto 0);
108 signal IRF_DAT_I : std_logic_vector (15 downto 0);
109 signal IRF_DAT_O : std_logic_vector (15 downto 0);
110 signal IRF_STB : std_logic;
111 signal IRF_WE : std_logic;
112 -- Wave look-up table
113 signal LUT_ADR : std_logic_vector (LUT_ADR_W-1 downto 0);
114 signal LUT_DAT_O : std_logic_vector (PWM_W-1 downto 0);
115 signal LUT_STB : std_logic;
116 -- MCC execution control
117 signal MCC_ACK : std_logic;
118 signal MCC_STB : std_logic;
120 ------------------------------------------------------------------------------
122 ------------------------------------------------------------------------------
123 signal PWM_CNT : std_logic_vector (PWM_W-1 downto 0);
124 signal PWM_OW : std_logic; -- PWM counter overflow
125 -- PWM interface to the MCC
126 signal PWM_DAT : std_logic_vector (PWM_W-1 downto 0);
127 signal PWM1_STB : std_logic;
128 signal PWM2_STB : std_logic;
129 signal PWM3_STB : std_logic;
131 signal PWM1_OUT : std_logic;
132 signal PWM2_OUT : std_logic;
133 signal PWM3_OUT : std_logic;
135 signal QCNT : std_logic_vector (31 downto 0);
137 --------------------------------------------------------------------------------
141 ------------------------------------------------------------------------------
142 -- OpenMSP430 softcore MCU module
143 ------------------------------------------------------------------------------
144 openMSP430_1 : entity work.openMSP430_8_32_mul_dbus
146 dco_clk => CLK_24MHz,
151 per_addr => per_addr,
153 per_dout => per_dout,
163 dmem_addr => dmem_addr,
166 dmem_din => dmem_din,
167 dmem_dout => dmem_dout);
170 reset_p <= not RESET;
172 STARTUP_VIRTEX2_inst : STARTUP_VIRTEX2
175 -- Clock input for start-up sequence
176 GSR => reset_p, -- Global Set/Reset input (GSR cannot be used for the port name)
177 GTS => open); -- Global 3-state input (GTS cannot be used for the port name)
180 -- External data bus address decoder and data multiplexer.
181 ------------------------------------------------------------------------------
182 -- When connection more memories, be aware that 'dmem_dout' can vary only when
183 -- reading cycle is performed. I.e. mux variable must be registered.
184 dmem_dout <= DPA_DAT_O;
186 DPA_SEL <= '1' when dmem_addr (11 downto 10) = "00" else '0';
187 DPA_STB <= dmem_ce and DPA_SEL;
189 -- Peripheral bus address decoder and data multiplexer.
190 ------------------------------------------------------------------------------
191 per_dout <= GPIO_DAT_O when GPIO_SEL = '1' else
192 QCNT_DAT_O when QCNT_SEL = '1' else
193 (others => '0'); -- MUST be 0 when nothing is addressed
195 GPIO_SEL <= '1' when per_addr(7 downto 2) = 16#0140#/2/4 else '0';
196 QCNT_SEL <= '1' when per_addr(7 downto 1) = 16#0148#/2/2 else '0';
199 ------------------------------------------------------------------------------
200 irq (13 downto 1) <= (others => '0');
202 motor_irq_gen : process (mclk, puc) is
204 if rising_edge (mclk) then
205 if puc = '1' or irq_acc (0) = '1' then
207 elsif MOTOR_IRQ = '1' then
214 ------------------------------------------------------------------------------
216 ------------------------------------------------------------------------------
220 GPIO_IN(3) <= IRC_INDEX;
222 gpio_0 : entity work.gpio
227 ADR_I => per_addr (1 downto 0),
238 qcounter_mcu16_0 : entity work.qcounter_mcu16
241 ADR_I => per_addr (0),
248 -- Motor feedback IRQ generator
249 -- f_motor_irq approx. 1 kHz
250 irq_counter_1 : entity work.counter
259 event_ow => MOTOR_IRQ);
262 ------------------------------------------------------------------------------
263 -- Dual-port shared memory
264 ------------------------------------------------------------------------------
265 -- Shared memory between MCU and MCC (size: 16+2 bits x 1k).
266 -- Port A (MCU side) has a priority of writing.
267 shared_mem : RAMB16_S18_S18
269 WRITE_MODE_A => "READ_FIRST",
270 WRITE_MODE_B => "WRITE_FIRST")
273 ADDRA => dmem_addr (9 downto 0),
293 -- B-Port address (10 bits) constructed from IRF_ADR (5 bits). Upper addr bits
294 -- are forced to '0', but in a case of several axes these can be used to
295 -- address memory space of the appropriate one.
296 DPB_ADR (9 downto 5) <= (others => '0');
297 DPB_ADR (4 downto 0) <= IRF_ADR;
299 -- Generation of IRF acknowledge signal for MCC.
300 IRF_ACK <= IRF_STB and (IRF_WE or IRF_ACK_REG);
302 -- IRF_ACK_REG signalizes that data is present on IRF_DAT_O when reading.
303 irf_read : process (mclk, puc) is
305 if rising_edge(mclk) then
309 IRF_ACK_REG <= IRF_STB and not IRF_WE;
315 ------------------------------------------------------------------------------
316 -- Motion Control Chain
317 ------------------------------------------------------------------------------
318 mcc_exec_1 : entity work.mcc_exec
328 MCC_EXEC_I => PWM_OW,
330 MCC_ACK_I => MCC_ACK,
331 MCC_STB_O => MCC_STB);
333 mcc_1 : entity work.mcc
336 LUT_ADR_W => LUT_ADR_W)
342 LUT_STB_O => LUT_STB,
343 LUT_ADR_O => LUT_ADR,
344 LUT_DAT_I => LUT_DAT_O,
345 IRC_DAT_I => QCNT (15 downto 0),
346 PWM_DAT_O => PWM_DAT,
347 PWM1_STB_O => PWM1_STB,
348 PWM2_STB_O => PWM2_STB,
349 PWM3_STB_O => PWM3_STB,
350 IRF_ACK_I => IRF_ACK,
351 IRF_ADR_O => IRF_ADR,
352 IRF_DAT_I => IRF_DAT_O,
353 IRF_DAT_O => IRF_DAT_I,
354 IRF_STB_O => IRF_STB,
357 wave_table_1 : entity work.wave_table
361 INIT_FILE => LUT_INIT)
366 DAT_I => conv_std_logic_vector(0, PWM_W),
372 ------------------------------------------------------------------------------
374 ------------------------------------------------------------------------------
375 -- PWM counter is shared by all PWM generators. Generator contains only
376 -- comparator and desired value.
377 pwm_counter : entity work.counter
388 pwm_1 : entity work.pwm
401 pwm_2 : entity work.pwm
414 pwm_3 : entity work.pwm
427 -- PWM signals mapped to FPGA outputs, EN forced to '1'
428 PWM0 <= not PWM1_OUT;
430 PWM1 <= not PWM2_OUT;
432 PWM2 <= not PWM3_OUT;
435 -- PWM is signalized on LEDs
440 qcounter_1 : entity work.qcounter