2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
7 use unisim.vcomponents.all;
9 --------------------------------------------------------------------------------
14 CLK_24MHz : in std_logic;
25 PWM0_EN : out std_logic;
27 PWM1_EN : out std_logic;
29 PWM2_EN : out std_logic;
31 IRC_INDEX : in std_logic;
40 --------------------------------------------------------------------------------
42 architecture rtl of msp_motion is
44 signal reset_p : std_logic;
46 ------------------------------------------------------------------------------
47 -- OpenMSP430 softcore MCU module
48 ------------------------------------------------------------------------------
49 signal mclk : std_logic;
50 signal puc : std_logic;
52 signal dmem_addr : std_logic_vector (11 downto 0);
53 signal dmem_ce : std_logic;
54 signal dmem_we : std_logic;
55 signal dmem_din : std_logic_vector (15 downto 0);
56 signal dmem_dout : std_logic_vector (15 downto 0);
58 signal per_din : std_logic_vector (15 downto 0);
59 signal per_dout : std_logic_Vector (15 downto 0);
60 signal per_wen : std_logic_vector (1 downto 0);
61 signal per_wen16 : std_logic;
62 signal per_en : std_logic;
63 signal per_addr : std_logic_vector (7 downto 0);
65 --signal irq : std_logic_vector (13 downto 0) := (others => '0');
66 signal irq : std_logic_vector (13 downto 0);
67 signal irq_acc : std_logic_vector (13 downto 0);
69 ------------------------------------------------------------------------------
71 ------------------------------------------------------------------------------
73 signal GPIO_IN : std_logic_vector (15 downto 0);
74 signal GPIO_OUT : std_logic_vector (15 downto 0);
75 signal GPIO_DAT_O : std_logic_vector (15 downto 0);
76 signal GPIO_SEL : std_logic;
77 -- Qcounter MCU interface
78 signal QCNT_DAT_O : std_logic_vector (15 downto 0);
79 signal QCNT_SEL : std_logic;
80 -- Motor feedback IRQ generator
81 signal MOTOR_IRQ : std_logic;
83 signal EVENT_DAT_O : std_logic_vector (15 downto 0);
84 signal EVENT_SEL : std_logic;
85 signal event_i : std_logic_vector (15 downto 0);
86 signal event_o : std_logic_vector (15 downto 0);
88 signal CAPTURE_SEL : std_logic;
89 signal CAPTURE_DAT : std_logic_vector (15 downto 0);
90 -- IRC index detection
91 signal INDEX_DETECT_DAT_O : std_logic_vector (15 downto 0);
92 signal INDEX_DETECT_SEL : std_logic;
94 ------------------------------------------------------------------------------
95 -- Dual-port shared memory
96 ------------------------------------------------------------------------------
97 -- These signals of A-port (MCU) enables creation of external data encoder and
98 -- multiplexer in a case of multiple devices connected to the external data
99 -- bus. Otherwise useless.
100 signal DPA_DAT_O : std_logic_vector (15 downto 0);
101 signal DPA_SEL : std_logic;
102 signal DPA_STB : std_logic;
103 -- Auxiliary register used to generate IRF_ACK
104 signal IRF_ACK_REG : std_logic := '0';
105 -- Auxiliary signal used to form B-port address
106 signal DPB_ADR : std_logic_vector (9 downto 0);
108 ------------------------------------------------------------------------------
109 -- Motion Control Chain
110 ------------------------------------------------------------------------------
112 constant PWM_W : integer := 10;
113 constant LUT_ADR_W : integer := 11;
114 constant LUT_INIT : string := "sin1000.lut";
116 -- Bus interface to the shared memory
117 signal IRF_ACK : std_logic;
118 signal IRF_ADR : std_logic_vector (4 downto 0);
119 signal IRF_DAT_I : std_logic_vector (15 downto 0);
120 signal IRF_DAT_O : std_logic_vector (15 downto 0);
121 signal IRF_STB : std_logic;
122 signal IRF_WE : std_logic;
123 -- Wave look-up table
124 signal LUT_ADR : std_logic_vector (LUT_ADR_W-1 downto 0);
125 signal LUT_DAT_O : std_logic_vector (PWM_W-1 downto 0);
126 signal LUT_STB : std_logic;
127 -- MCC execution control
128 signal MCC_ACK : std_logic;
129 signal MCC_STB : std_logic;
131 ------------------------------------------------------------------------------
133 ------------------------------------------------------------------------------
134 signal PWM_CNT : std_logic_vector (PWM_W-1 downto 0);
135 signal PWM_OW : std_logic; -- PWM counter overflow
136 -- PWM interface to the MCC
137 signal PWM_DAT : std_logic_vector (PWM_W-1 downto 0);
138 signal PWM1_STB : std_logic;
139 signal PWM2_STB : std_logic;
140 signal PWM3_STB : std_logic;
142 signal PWM1_OUT : std_logic;
143 signal PWM2_OUT : std_logic;
144 signal PWM3_OUT : std_logic;
146 signal QCNT : std_logic_vector (31 downto 0);
148 signal IRC_INDEX_DFF : std_logic; -- IRC_INDEX aligned with global clock
149 signal IRC_INDEX_EVENT : std_logic;
151 --------------------------------------------------------------------------------
155 ------------------------------------------------------------------------------
156 -- OpenMSP430 softcore MCU module
157 ------------------------------------------------------------------------------
158 openMSP430_1 : entity work.openMSP430_8_32_mul_dbus
160 dco_clk => CLK_24MHz,
165 per_addr => per_addr,
167 per_dout => per_dout,
177 dmem_addr => dmem_addr,
180 dmem_din => dmem_din,
181 dmem_dout => dmem_dout);
184 reset_p <= not RESET;
186 STARTUP_VIRTEX2_inst : STARTUP_VIRTEX2
189 -- Clock input for start-up sequence
190 GSR => reset_p, -- Global Set/Reset input (GSR cannot be used for the port name)
191 GTS => open); -- Global 3-state input (GTS cannot be used for the port name)
194 -- External data bus address decoder and data multiplexer.
195 ------------------------------------------------------------------------------
196 -- When connection more memories, be aware that 'dmem_dout' can vary only when
197 -- reading cycle is performed. I.e. mux variable must be registered.
198 dmem_dout <= DPA_DAT_O;
200 DPA_SEL <= '1' when dmem_addr (11 downto 10) = "00" else '0';
201 DPA_STB <= dmem_ce and DPA_SEL;
203 -- Peripheral bus address decoder and data multiplexer.
204 ------------------------------------------------------------------------------
205 per_dout <= GPIO_DAT_O when GPIO_SEL = '1' else
206 QCNT_DAT_O when QCNT_SEL = '1' else
207 EVENT_DAT_O when EVENT_SEL = '1' else
208 CAPTURE_DAT when CAPTURE_SEL = '1' else
209 INDEX_DETECT_DAT_O when INDEX_DETECT_SEL ='1' else
210 (others => '0'); -- MUST be 0 when nothing is addressed
212 GPIO_SEL <= '1' when per_addr(7 downto 2) = 16#0140#/2/4 else '0';
213 QCNT_SEL <= '1' when per_addr(7 downto 1) = 16#0148#/2/2 else '0';
214 EVENT_SEL <= '1' when per_addr(7 downto 0) = 16#014C#/2 else '0';
215 CAPTURE_SEL <= '1' when per_addr(7 downto 1) = 16#0150#/2/2 else '0';
216 INDEX_DETECT_SEL <= '1' when per_addr(7 downto 1) = 16#0152#/2/2 else '0';
218 per_wen16 <= per_wen(0) and per_wen(1);
221 ------------------------------------------------------------------------------
222 irq (13 downto 1) <= (others => '0');
224 motor_irq_gen : process (mclk, puc) is
226 if rising_edge (mclk) then
227 if puc = '1' or irq_acc (0) = '1' then
229 elsif MOTOR_IRQ = '1' then
236 ------------------------------------------------------------------------------
238 ------------------------------------------------------------------------------
242 GPIO_IN(3) <= IRC_INDEX;
244 gpio_0 : entity work.gpio
249 ADR_I => per_addr (1 downto 0),
260 qcounter_mcu16_0 : entity work.qcounter_mcu16
263 ADR_I => per_addr (0),
270 -- Motor feedback IRQ generator
271 -- f_motor_irq approx. 1 kHz
272 irq_counter_1 : entity work.counter
281 event_ow => MOTOR_IRQ);
283 event_io_0 : entity work.event_rwc
285 -- Peripheral bus interface
289 DAT_O => EVENT_DAT_O,
298 event_i(0) <= (not IRC_INDEX_DFF) and (not event_o(0));
299 IRC_INDEX_EVENT <= event_i(0);
302 irc_index_dff_0 : entity work.dff
308 capture_reg16_0 : entity work.capture_reg16
311 ADR_I => per_addr (0 downto 0),
313 DAT_O => CAPTURE_DAT,
314 SEL_I => CAPTURE_SEL,
316 EVENT_I => IRC_INDEX_EVENT,
319 ------------------------------------------------------------------------------
320 -- Dual-port shared memory
321 ------------------------------------------------------------------------------
322 -- Shared memory between MCU and MCC (size: 16+2 bits x 1k).
323 -- Port A (MCU side) has a priority of writing.
324 shared_mem : RAMB16_S18_S18
326 WRITE_MODE_A => "READ_FIRST",
327 WRITE_MODE_B => "WRITE_FIRST")
330 ADDRA => dmem_addr (9 downto 0),
350 -- B-Port address (10 bits) constructed from IRF_ADR (5 bits). Upper addr bits
351 -- are forced to '0', but in a case of several axes these can be used to
352 -- address memory space of the appropriate one.
353 DPB_ADR (9 downto 5) <= (others => '0');
354 DPB_ADR (4 downto 0) <= IRF_ADR;
356 -- Generation of IRF acknowledge signal for MCC.
357 IRF_ACK <= IRF_STB and (IRF_WE or IRF_ACK_REG);
359 -- IRF_ACK_REG signalizes that data is present on IRF_DAT_O when reading.
360 irf_read : process (mclk, puc) is
362 if rising_edge(mclk) then
366 IRF_ACK_REG <= IRF_STB and not IRF_WE;
372 ------------------------------------------------------------------------------
373 -- Motion Control Chain
374 ------------------------------------------------------------------------------
375 mcc_exec_1 : entity work.mcc_exec
385 MCC_EXEC_I => PWM_OW,
387 MCC_ACK_I => MCC_ACK,
388 MCC_STB_O => MCC_STB);
390 mcc_1 : entity work.mcc
393 LUT_ADR_W => LUT_ADR_W)
399 LUT_STB_O => LUT_STB,
400 LUT_ADR_O => LUT_ADR,
401 LUT_DAT_I => LUT_DAT_O,
402 IRC_DAT_I => QCNT (15 downto 0),
403 PWM_DAT_O => PWM_DAT,
404 PWM1_STB_O => PWM1_STB,
405 PWM2_STB_O => PWM2_STB,
406 PWM3_STB_O => PWM3_STB,
407 IRF_ACK_I => IRF_ACK,
408 IRF_ADR_O => IRF_ADR,
409 IRF_DAT_I => IRF_DAT_O,
410 IRF_DAT_O => IRF_DAT_I,
411 IRF_STB_O => IRF_STB,
414 wave_table_1 : entity work.wave_table
418 INIT_FILE => LUT_INIT)
423 DAT_I => conv_std_logic_vector(0, PWM_W),
429 ------------------------------------------------------------------------------
431 ------------------------------------------------------------------------------
432 -- PWM counter is shared by all PWM generators. Generator contains only
433 -- comparator and desired value.
434 pwm_counter : entity work.counter
445 pwm_1 : entity work.pwm
458 pwm_2 : entity work.pwm
471 pwm_3 : entity work.pwm
484 -- PWM signals mapped to FPGA outputs, EN forced to '1'
485 PWM0 <= not PWM1_OUT;
487 PWM1 <= not PWM2_OUT;
489 PWM2 <= not PWM3_OUT;
492 -- PWM is signalized on LEDs
497 qcounter_1 : entity work.qcounter