process (clk, reset)
begin
- if (reset = '1') then
- counter <= (others => '0');
- clk_baud_s <= '0';
-
- elsif (rising_edge(clk)) then
- if (clk_baud_s = '0' and ce = '0') then
+ if (rising_edge(clk)) then
+ if (reset = '1') then
counter <= (others => '0');
+ clk_baud_s <= '0';
else
- if (counter = 0) then
- counter <= scale;
- clk_baud_s <= not clk_baud_s;
+ if (clk_baud_s = '0' and ce = '0') then
+ counter <= (others => '0');
else
- counter <= counter - 1;
+ if (counter = 0) then
+ counter <= scale;
+ clk_baud_s <= not clk_baud_s;
+ else
+ counter <= counter - 1;
+
+ end if;
end if;
end if;
end if;
-- the number of occupied memory positions.
process (clk, reset)
begin
- if (reset = '1') then
- length <= (others => '0');
- overflow <= '0';
-
- elsif (rising_edge(clk)) then
- if ((re = '1') and (we = '0')) then
- length <= length - 1;
- elsif ((re = '0') and (we = '1')) then
- if (full_s = '1') then
- overflow <= '1';
- else
- length <= length + 1;
- end if;
- end if;
-
- if (clear_ow = '1') then
+ if (rising_edge(clk)) then
+ if (reset = '1') then
+ length <= (others => '0');
overflow <= '0';
+
+ else
+ if ((re = '1') and (we = '0')) then
+ length <= length - 1;
+ elsif ((re = '0') and (we = '1')) then
+ if (full_s = '1') then
+ overflow <= '1';
+ else
+ length <= length + 1;
+ end if;
+ end if;
+
+ if (clear_ow = '1') then
+ overflow <= '0';
+ end if;
end if;
end if;
end process;
process (clk, reset) is
begin
- if reset = '1' then
- rx_ready <= '1';
- rx_running <= '0';
-
- bad_stop_bit <= '0';
- bad_start_bit <= '0';
+ if clk'event and clk = '0' then
+ if reset = '1' then
+ rx_ready <= '1';
+ rx_running <= '0';
+
+ bad_stop_bit <= '0';
+ bad_start_bit <= '0';
- elsif clk'event and clk = '0' then
- -- Start receiving a new frame
- if rx_ready = '1' and en = '1' then
- rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
- rx_flag <= "0100000000";
- rx_ready <= '0';
- rx_running <= '1';
+ else
+ -- Start receiving a new frame
+ if rx_ready = '1' and en = '1' then
+ rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
+ rx_flag <= "0100000000";
+ rx_ready <= '0';
+ rx_running <= '1';
- bad_start_bit <= rx;
- bad_stop_bit <= '0';
+ bad_start_bit <= rx;
+ bad_stop_bit <= '0';
- -- Receiving of the 1st data bit and all its consequents
- elsif rx_running = '1' then
- rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
- rx_flag <= '0' & rx_flag (9 downto 1);
+ -- Receiving of the 1st data bit and all its consequents
+ elsif rx_running = '1' then
+ rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
+ rx_flag <= '0' & rx_flag (9 downto 1);
- -- End of the frame is comming
- if rx_flag (0) = '1' then
- rx_ready <= '1';
- rx_running <= '0';
+ -- End of the frame is comming
+ if rx_flag (0) = '1' then
+ rx_ready <= '1';
+ rx_running <= '0';
- bad_stop_bit <= not rx;
+ bad_stop_bit <= not rx;
+ end if;
end if;
end if;
-
end if;
end process;
process (clk, reset) is
begin
- if reset = '1' then
- state <= waiting;
- rx_reset <= '0';
- rx_en <= '0';
- fifo_we <= '0';
- clk_en <= '0';
-
- elsif clk'event and clk = '1' then
- case state is
- when resetting =>
- state <= waiting;
- rx_reset <= '0';
- rx_en <= '0';
- fifo_we <= '0';
- clk_en <= '0';
-
-
- when waiting =>
- rx_reset <= '0';
- rx_en <= '0';
- fifo_we <= '0';
- clk_en <= '0';
-
- if rx = '0' then
- state <= next_frame;
- rx_en <= '1';
- clk_en <= '1';
- end if;
-
-
- when next_frame =>
- rx_reset <= '0';
- rx_en <= '1';
- fifo_we <= '0';
- clk_en <= '1';
-
- if rx_ready = '0' then
- if bad_start_bit = '1' then
- state <= resetting;
- rx_reset <= '1';
- rx_en <= '0';
- clk_en <= '0';
-
- else
- state <= receiving;
- rx_en <= '0';
+ if clk'event and clk = '1' then
+ if reset = '1' then
+ state <= waiting;
+ rx_reset <= '0';
+ rx_en <= '0';
+ fifo_we <= '0';
+ clk_en <= '0';
+
+ else
+ case state is
+ when resetting =>
+ state <= waiting;
+ rx_reset <= '0';
+ rx_en <= '0';
+ fifo_we <= '0';
+ clk_en <= '0';
+
+
+ when waiting =>
+ rx_reset <= '0';
+ rx_en <= '0';
+ fifo_we <= '0';
+ clk_en <= '0';
+
+ if rx = '0' then
+ state <= next_frame;
+ rx_en <= '1';
+ clk_en <= '1';
end if;
- end if;
- when receiving =>
- rx_reset <= '0';
- rx_en <= '0';
- fifo_we <= '0';
- clk_en <= '1';
+ when next_frame =>
+ rx_reset <= '0';
+ rx_en <= '1';
+ fifo_we <= '0';
+ clk_en <= '1';
- if rx_ready = '1' then
- state <= waiting;
- fifo_we <= '1';
- clk_en <= '0';
- end if;
+ if rx_ready = '0' then
+ if bad_start_bit = '1' then
+ state <= resetting;
+ rx_reset <= '1';
+ rx_en <= '0';
+ clk_en <= '0';
- end case;
+ else
+ state <= receiving;
+ rx_en <= '0';
+ end if;
+ end if;
+
+
+ when receiving =>
+ rx_reset <= '0';
+ rx_en <= '0';
+ fifo_we <= '0';
+ clk_en <= '1';
+
+ if rx_ready = '1' then
+ state <= waiting;
+ fifo_we <= '1';
+ clk_en <= '0';
+ end if;
+
+ end case;
+ end if;
end if;
end process;
process (clk, reset)
begin
- if (reset = '1') then
- tx_shift_reg <= "1111111111";
- tx_flag <= "0000000000";
- tx_ready <= '1';
+ if (rising_edge(clk)) then
+ if (reset = '1') then
+ tx_shift_reg <= "1111111111";
+ tx_flag <= "0000000000";
+ tx_ready <= '1';
- elsif (rising_edge(clk)) then
- if (we = '1') then
- tx_shift_reg <= '1' & data & '0';
- tx_flag <= "1000000000";
- tx_ready <= '0';
-
- else
- tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
- tx_flag <= '0' & tx_flag(9 downto 1);
-
- if (tx_flag(1) = '1') then
- tx_ready <= '1';
+ else
+ if (we = '1') then
+ tx_shift_reg <= '1' & data & '0';
+ tx_flag <= "1000000000";
+ tx_ready <= '0';
+
+ else
+ tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
+ tx_flag <= '0' & tx_flag(9 downto 1);
+
+ if (tx_flag(1) = '1') then
+ tx_ready <= '1';
+ end if;
+
end if;
-
end if;
end if;
end process;
process (clk, reset)
begin
- if (reset = '1') then
- state <= waiting;
-
- elsif (rising_edge(clk)) then
- case state is
- when waiting =>
- if (fifo_empty = '0') then
- state <= next_frame;
- end if;
-
- when next_frame =>
- if (tx_ready = '0') then
- state <= transmitting;
- end if;
-
- when transmitting =>
- if (tx_ready = '1') then
+ if (rising_edge(clk)) then
+ if (reset = '1') then
+ state <= waiting;
+
+ else
+ case state is
+ when waiting =>
if (fifo_empty = '0') then
state <= next_frame;
- else
- state <= waiting;
end if;
- end if;
- end case;
+
+ when next_frame =>
+ if (tx_ready = '0') then
+ state <= transmitting;
+ end if;
+
+ when transmitting =>
+ if (tx_ready = '1') then
+ if (fifo_empty = '0') then
+ state <= next_frame;
+ else
+ state <= waiting;
+ end if;
+ end if;
+ end case;
+ end if;
end if;
end process;
process (mclk, puc) is
begin
- if puc = '1' then
- reg_baud <= (others => '0');
- reg_ie <= (others => '0');
-
- elsif mclk'event and mclk = '1' then
- if reg_we (UBAUD) = '1' then
- reg_baud (7 downto 0) <= per_din_low;
- end if;
+ if mclk'event and mclk = '1' then
+ if puc = '1' then
+ reg_baud <= (others => '0');
+ reg_ie <= (others => '0');
+
+ else
+ if reg_we (UBAUD) = '1' then
+ reg_baud (7 downto 0) <= per_din_low;
+ end if;
- if reg_we (UBAUD+1) = '1' then
- reg_baud (15 downto 8) <= per_din_high;
- end if;
+ if reg_we (UBAUD+1) = '1' then
+ reg_baud (15 downto 8) <= per_din_high;
+ end if;
- if reg_we (USTAT) = '1' then
- reg_ie <= per_din_low;
+ if reg_we (USTAT) = '1' then
+ reg_ie <= per_din_low;
+ end if;
end if;
end if;
end process;