rtime.felk.cvut.cz Git - fpga/uart.git/history

]> rtime.felk.cvut.cz Git - fpga/uart.git/history - rx.vhd

2011-05-18	Vladimir Burian	Resets changed from asynchronous to synchronous. master	blob \| commitdiff \| raw
2011-05-18	Vladimir Burian	Early initialization of all relevant signals.	blob \| commitdiff \| raw \| diff to current
2011-02-04	Vladimir Burian	RX modul synchronization changed to falling edges.	blob \| commitdiff \| raw \| diff to current
2011-02-04	Vladimir Burian	First prototype of receiver shift register.	blob \| commitdiff \| raw \| diff to current

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