zmena hodin pro spi z SCLK (500kHz) na GPCLK (2,4MHZ). Pomoci GPCLK je nyni 'vzorkova...

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index d3f69bceb7bb6b0c52a0eb80633edccdaa0de5bf..7b4ef787cb28637488cdbb054697441f94c8f733 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -20,7 +20,7 @@ entity rpi_mc_simple_dc is
        port (
                gpio2: in std_logic; -- SDA
                gpio3: in std_logic; -- SCL
-               gpio4: out std_logic; -- CLK
+               gpio4: in std_logic; -- CLK
                gpio14: in std_logic; -- Tx
                gpio15: in std_logic; -- Rx
                gpio17: out std_logic; -- RTS
@@ -103,8 +103,10 @@ architecture behavioral of rpi_mc_simple_dc is
                port (A: in std_logic; Y: out std_logic);
        end component;
 
+       signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin
        signal pwm_in, pwm_dir_in: std_logic;
        signal spi_clk: std_logic;
+       signal gpio_clk: std_logic;
        signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); --registr pro SPI
 
        --  attribute syn_noprune of gpio2 : signal is true;
@@ -114,11 +116,21 @@ architecture behavioral of rpi_mc_simple_dc is
 
 begin
        -- PLL as a reset generator
+       
+       --zesileni signalu hodin SPI - bez zesileni nelze syntetizovat
        copyclk: CLKINT
        port map (
                a => gpio11,
                y => spi_clk
        );
+       
+       --zesileni signalu GPIO CLK
+       copyclk2: CLKINT
+       port map (
+               a => gpio4,
+               y => gpio_clk
+       );
+       
        --   pll: pll50to200
        --     port map (
        --       powerdown => '1',
@@ -130,7 +142,7 @@ begin
                                            -- upon power-on
        --   clock <= clkm;
 
-       dummy_unused <= gpio2 and gpio3  and
+       dummy_unused <= gpio2 and gpio3  and gpio4 and
                gpio5 and gpio6 and
                gpio12 and gpio13 and gpio14 and
                gpio15 and gpio16 and gpio19 and
@@ -163,20 +175,21 @@ begin
 
 
   
-       process (spi_clk) --nufunguje preo piny 11,17,27 funguje pro 4,18,22,ext_sclk,10
+       process (gpio_clk) 
        begin
                --if (gpio11'event and gpio11 = '1') then  -- rising edge of SCK
-               if (rising_edge(spi_clk)) then 
+               if ((spi_clk = '1') and (spiclk_old_lvl = '0') ) then 
                        if (gpio7 = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first
                                dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
-                
+                               spiclk_old_lvl <= '1';
        
                        end if;
-               elsif (falling_edge(spi_clk)) then
+               elsif ((spi_clk = '0') and (spiclk_old_lvl = '1')) then
                        if (gpio7 = '0') then
                                gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
+                               spiclk_old_lvl <= '0';
                        end if;
                end if;
        end process;