1 -- Version: 9.1 9.1.0.18
4 use ieee.std_logic_1164.all;
9 port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out
14 architecture DEF_ARCH of pll50to200 is
17 generic (VCOFREQUENCY:real := 0.0);
19 port(CLKA, EXTFB, POWERDOWN : in std_logic := 'U'; GLA,
20 LOCK, GLB, YB, GLC, YC : out std_logic; OADIV0, OADIV1,
21 OADIV2, OADIV3, OADIV4, OAMUX0, OAMUX1, OAMUX2, DLYGLA0,
22 DLYGLA1, DLYGLA2, DLYGLA3, DLYGLA4, OBDIV0, OBDIV1,
23 OBDIV2, OBDIV3, OBDIV4, OBMUX0, OBMUX1, OBMUX2, DLYYB0,
24 DLYYB1, DLYYB2, DLYYB3, DLYYB4, DLYGLB0, DLYGLB1, DLYGLB2,
25 DLYGLB3, DLYGLB4, OCDIV0, OCDIV1, OCDIV2, OCDIV3, OCDIV4,
26 OCMUX0, OCMUX1, OCMUX2, DLYYC0, DLYYC1, DLYYC2, DLYYC3,
27 DLYYC4, DLYGLC0, DLYGLC1, DLYGLC2, DLYGLC3, DLYGLC4,
28 FINDIV0, FINDIV1, FINDIV2, FINDIV3, FINDIV4, FINDIV5,
29 FINDIV6, FBDIV0, FBDIV1, FBDIV2, FBDIV3, FBDIV4, FBDIV5,
30 FBDIV6, FBDLY0, FBDLY1, FBDLY2, FBDLY3, FBDLY4, FBSEL0,
31 FBSEL1, XDLYSEL, VCOSEL0, VCOSEL1, VCOSEL2 : in std_logic :=
36 port( Y : out std_logic);
40 port( Y : out std_logic);
43 signal VCC_1_net, GND_1_net : std_logic ;
46 VCC_2_net : VCC port map(Y => VCC_1_net);
47 GND_2_net : GND port map(Y => GND_1_net);
49 generic map(VCOFREQUENCY => 200.000)
51 port map(CLKA => CLKA, EXTFB => GND_1_net, POWERDOWN =>
52 POWERDOWN, GLA => GLA, LOCK => LOCK, GLB => OPEN , YB =>
53 OPEN , GLC => OPEN , YC => OPEN , OADIV0 => GND_1_net,
54 OADIV1 => GND_1_net, OADIV2 => GND_1_net, OADIV3 =>
55 GND_1_net, OADIV4 => GND_1_net, OAMUX0 => GND_1_net,
56 OAMUX1 => GND_1_net, OAMUX2 => VCC_1_net, DLYGLA0 =>
57 GND_1_net, DLYGLA1 => GND_1_net, DLYGLA2 => GND_1_net,
58 DLYGLA3 => GND_1_net, DLYGLA4 => GND_1_net, OBDIV0 =>
59 GND_1_net, OBDIV1 => GND_1_net, OBDIV2 => GND_1_net,
60 OBDIV3 => GND_1_net, OBDIV4 => GND_1_net, OBMUX0 =>
61 GND_1_net, OBMUX1 => GND_1_net, OBMUX2 => GND_1_net,
62 DLYYB0 => GND_1_net, DLYYB1 => GND_1_net, DLYYB2 =>
63 GND_1_net, DLYYB3 => GND_1_net, DLYYB4 => GND_1_net,
64 DLYGLB0 => GND_1_net, DLYGLB1 => GND_1_net, DLYGLB2 =>
65 GND_1_net, DLYGLB3 => GND_1_net, DLYGLB4 => GND_1_net,
66 OCDIV0 => GND_1_net, OCDIV1 => GND_1_net, OCDIV2 =>
67 GND_1_net, OCDIV3 => GND_1_net, OCDIV4 => GND_1_net,
68 OCMUX0 => GND_1_net, OCMUX1 => GND_1_net, OCMUX2 =>
69 GND_1_net, DLYYC0 => GND_1_net, DLYYC1 => GND_1_net,
70 DLYYC2 => GND_1_net, DLYYC3 => GND_1_net, DLYYC4 =>
71 GND_1_net, DLYGLC0 => GND_1_net, DLYGLC1 => GND_1_net,
72 DLYGLC2 => GND_1_net, DLYGLC3 => GND_1_net, DLYGLC4 =>
73 GND_1_net, FINDIV0 => VCC_1_net, FINDIV1 => GND_1_net,
74 FINDIV2 => GND_1_net, FINDIV3 => VCC_1_net, FINDIV4 =>
75 GND_1_net, FINDIV5 => GND_1_net, FINDIV6 => GND_1_net,
76 FBDIV0 => VCC_1_net, FBDIV1 => VCC_1_net, FBDIV2 =>
77 VCC_1_net, FBDIV3 => GND_1_net, FBDIV4 => GND_1_net,
78 FBDIV5 => VCC_1_net, FBDIV6 => GND_1_net, FBDLY0 =>
79 GND_1_net, FBDLY1 => GND_1_net, FBDLY2 => GND_1_net,
80 FBDLY3 => GND_1_net, FBDLY4 => GND_1_net, FBSEL0 =>
81 VCC_1_net, FBSEL1 => GND_1_net, XDLYSEL => GND_1_net,
82 VCOSEL0 => VCC_1_net, VCOSEL1 => VCC_1_net, VCOSEL2 =>
86 -- _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._
89 -- _GEN_File_Contents_
96 -- LPMTYPE:LPM_PLL_STATIC
100 -- GEN_BHV_VHDL_VAL:F
101 -- GEN_BHV_VERILOG_VAL:F
104 -- DESDIR:/tmp/igloo/pll50to200
106 -- SMARTGEN_DIE:IS4X4M1LP
107 -- SMARTGEN_PACKAGE:vq100
108 -- AGENIII_IS_SUBPROJECT_LIBERO:F
114 -- PRIMFREQ:200.000000
118 -- POWERDOWN_POLARITY:0