1 -- provides frequency division by 256 (8 bit divider)
4 use ieee.std_logic_1164.all;
5 use ieee.numeric_std.all;
17 architecture behavioral of div256 is
18 signal count : std_logic_vector (8 downto 0);
25 wait until (clk_in'event and clk_in='1');
26 count <= std_logic_vector(unsigned(count) + 1);