1 -- provides frequency division by 12
2 -- initialy intended to make 4.17Mhz from 50Mhz
5 use ieee.std_logic_1164.all;
6 use ieee.numeric_std.all;
14 fail_safe: out std_logic
19 architecture behavioral of div128 is
20 signal count : std_logic_vector (6 downto 0);
21 signal rst_prev: std_logic;
27 wait until (clk_in'event and clk_in='1');
29 if rst='1' and rst_prev='0' then
33 count <= std_logic_vector(unsigned(count) + 1);
36 if count = "1111111" then