2 -- * Raspberry Pi BLDC/PMSM motor control design for RPi-MI-1 board *
3 -- SPI connected multichannel current ADC read and averaging
5 -- (c) 2015 Martin Prudek <prudemar@fel.cvut.cz>
6 -- Czech Technical University in Prague
8 -- Project supervision and original project idea
9 -- idea by Pavel Pisa <pisa@cmp.felk.cvut.cz>
11 -- Related RPi-MI-1 hardware is designed by Petr Porazil,
12 -- PiKRON Ltd <http://www.pikron.com>
14 -- license: GNU LGPL and GPLv3+
18 use ieee.std_logic_1164.all;
19 use ieee.numeric_std.all;
24 clk: in std_logic; --synchronous master clk
25 divided_clk : in std_logic; --divided clk - value suitable to sourcing voltage
26 adc_reset: in std_logic; --synchronous reset on rising edge
28 adc_miso: in std_logic; --spi master in slave out
29 adc_sclk: out std_logic; --spi clk
30 adc_scs: out std_logic; --spi slave select
31 adc_mosi: out std_logic; --spi master out slave in
33 adc_channels: out std_logic_vector (71 downto 0); --consistent data of 3 channels
34 measur_count: out std_logic_vector(8 downto 0) --number of accumulated measurments
40 architecture behavioral of adc_reader is
43 type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
44 signal state : state_type;
46 type channel_type is (ch0, ch1, ch2);
48 signal adc_data: std_logic_vector(11 downto 0);
49 signal adc_rst_prev : std_logic;
50 signal adc_address: std_logic_vector(2 downto 0);
51 signal cumul_data: std_logic_vector(71 downto 0); --unconsistent data, containing different amounts of measurments
52 signal prepared_data: std_logic_vector(71 downto 0); --consistent data, waiting for clk sync to propagate to output
53 signal m_count_sig: std_logic_vector(8 downto 0); --measurments count waiting for clk to propagate to output
54 signal first_pass: std_logic;
55 signal div_clk_prev: std_logic;
60 variable channel: channel_type;
61 variable reset_re: std_logic:='0';
62 variable reset_count: std_logic_vector (3 downto 0);
64 wait until (clk'event and clk='1');
66 --rising edge detection of reset signal
67 adc_rst_prev<=adc_reset;
68 if (adc_rst_prev='0') and (adc_reset='1') then
72 --rising edge detection of divided clk signal
73 div_clk_prev<=divided_clk;
74 if (divided_clk='1') and (div_clk_prev='0') then
78 reset_re:='0'; --clear reset flag
79 adc_scs<='1'; --active-low SS
80 adc_sclk<='0'; --lower clock
81 first_pass<='1'; --mark data as unprepared
82 channel:=ch0; --prepare channel0
83 adc_data<=(others=>'0'); --null working data
84 cumul_data<=(others=>'0'); --null working data
85 prepared_data<=(others=>'0'); --null the output
86 adc_channels<=(others=>'0'); --null the output
87 measur_count<=(others=>'0'); --null the count
88 m_count_sig<=(others=>'0'); --null the count
89 adc_address<="001"; --set its address
93 if (reset_count/="1111") then
94 reset_count:=std_logic_vector(unsigned(reset_count)+1);
95 --give the adc some time to prepare before transfer
96 adc_scs<=not reset_count(3);
100 when f1=> --1st 'fallin edge' - its not falling edge in any case-if rst clock is low before
102 adc_mosi<='1'; --start bit
103 state<=r1; --next state
104 when r1=> --1st rising edge (adc gets the start bit, we get date..)
106 adc_data(5)<=adc_miso;
108 when f2=> --2nd falling edge
110 adc_mosi<=adc_address(2); --A2 address
112 when r2=> --2nd rising edge (adc gets A2 address)
114 adc_data(4)<=adc_miso;
116 when f3=> --3rd falling edge
118 adc_mosi<=adc_address(1); --A1 address
120 when r3=> --rising edge
122 adc_data(3)<=adc_miso;
124 when f4=> --4th falling edge
126 adc_mosi<=adc_address(0); --A0 address
128 when r4=> --rising edge
130 adc_data(2)<=adc_miso;
132 when f5=> --5th falling edge
134 adc_mosi<='0'; --MODE (LOW -12bit)
136 when r5=> --rising edge
138 adc_data(1)<=adc_miso;
140 when f6=> --6th falling edge
142 adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
144 when r6=> --6th rising edge (we read last bit of conversion, adc gets SGL/DIF)
146 adc_data(0)<=adc_miso;
148 when f7=> -- 7th falling edge
150 adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
152 when r7=> --7th rising edge, data ready
154 if (first_pass='0') then
155 --add the current current to sum and shift the register
156 cumul_data(71 downto 0)<=
157 std_logic_vector(unsigned(cumul_data(47 downto 24))
158 +unsigned(adc_data(11 downto 0)))
159 & cumul_data(23 downto 0)
160 & cumul_data(71 downto 48);
163 when f8=> --8th falling edge
166 if (first_pass='0') then
169 adc_address<="101"; --ch1 address
170 channel:=ch1; --next channel code
172 adc_address<="010"; --ch2 address
173 channel:=ch2; --next channel code
175 --data order schould be: ch2 downto ch0 downto ch1
176 prepared_data(71 downto 0)<=cumul_data(71 downto 0);
177 m_count_sig<=std_logic_vector(unsigned(m_count_sig)+1);
178 adc_address<="001"; --ch0 address
179 channel:=ch0; --next channel code
183 when r8=> --8th rising edge (adc gets PD0), we propagate our results to output
185 adc_channels <= prepared_data; --data
186 measur_count <= m_count_sig; --count of measurments
187 first_pass<='0'; --data in next cycle are usable
189 when f9=> --9th falling edge busy state between conversion (we write nothing)
192 when r9=> --9th rising edge (we nor ads get nothing)
195 when f10=> --10th falling edge
198 when r10=> --10th rising edge (we read 1. bit of new conversion)
200 adc_data(11)<=adc_miso;
205 when r11=> --11th rising edge
207 adc_data(10)<=adc_miso;
212 when r12=> --12th rising edge
214 adc_data(9)<=adc_miso;
219 when r13=> --13th rising edge
221 adc_data(8)<=adc_miso;
226 when r14=> --14th rising edge
228 adc_data(7)<=adc_miso;
233 when r15=> --15th rising edge
235 adc_data(6)<=adc_miso;
236 if (reset_re='1') then --we check rising edge of reset