4 use ieee.std_logic_1164.all;
5 use ieee.numeric_std.all;
10 clk: in std_logic; --input clk
11 adc_reset: in std_logic;
12 adc_miso: in std_logic; --spi master in slave out
13 adc_channels: out std_logic_vector (35 downto 0); --consistent data of 3 channels
14 adc_sclk: out std_logic; --spi clk
15 adc_scs: out std_logic; --spi slave select
16 adc_mosi: out std_logic --spi master out slave in
22 architecture behavioral of adc_reader is
25 type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
26 signal state : state_type;
28 type channel_type is (ch0, ch1, ch2);
30 signal adc_data: std_logic_vector(11 downto 0);
31 signal adc_rst_old : std_logic_vector(1 downto 0);
32 signal adc_address: std_logic_vector(2 downto 0);
37 variable data_ready : std_logic;
38 variable channel: channel_type;
39 variable reset_re: std_logic:='0';
40 variable reset_count: std_logic_vector (3 downto 0);
42 wait until (clk'event and clk='1');
44 --rising edge detection of reset signal
45 adc_rst_old(0)<=adc_reset;
46 adc_rst_old(1)<=adc_rst_old(0);
48 if (adc_rst_old="01") then
54 reset_re:='0'; --clear reset flag
55 adc_scs<='1'; --active-low SS
56 adc_sclk<='0'; --lower clock
57 data_ready:='0'; --mark data as unprepared
58 channel:=ch0; --prepare channel0
59 adc_address<="001"; --set its address
63 if (reset_count/="1111") then
64 reset_count:=std_logic_vector(unsigned(reset_count)+1);
65 --give the adc some time to prepare before transfer
66 adc_scs<=not reset_count(3);
70 when f1=> --1st 'fallin edge' - its not falling edge in any case-if rst clock is low before
72 adc_mosi<='1'; --start bit
73 state<=r1; --next state
74 when r1=> --1st rising edge (adc gets the start bit, we get date..)
76 adc_data(5)<=adc_miso;
78 when f2=> --2nd falling edge
80 adc_mosi<=adc_address(2); --A2 address
82 when r2=> --2nd rising edge (adc gets A2 address)
84 adc_data(4)<=adc_miso;
86 when f3=> --3rd falling edge
88 adc_mosi<=adc_address(1); --A1 address
90 when r3=> --rising edge
92 adc_data(3)<=adc_miso;
94 when f4=> --4th falling edge
96 adc_mosi<=adc_address(0); --A0 address
98 when r4=> --rising edge
100 adc_data(2)<=adc_miso;
102 when f5=> --5th falling edge
104 adc_mosi<='0'; --MODE (LOW -12bit)
106 when r5=> --rising edge
108 adc_data(1)<=adc_miso;
110 when f6=> --6th falling edge
112 adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
114 when r6=> --6th rising edge (we read last bit of conversion, adc gets SGL/DIF)
116 adc_data(0)<=adc_miso;
118 when f7=> -- 7th falling edge
120 adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
122 when r7=> --7th rising edge, data ready
124 if (data_ready='1') then
127 adc_channels(35 downto 24)<=adc_data(11 downto 0);
128 adc_address<="101"; --ch1 address
131 adc_channels(23 downto 12)<=adc_data(11 downto 0);
132 adc_address<="010"; --ch2 address
135 adc_channels(11 downto 0)<=adc_data(11 downto 0);
136 adc_address<="001"; --ch0 address
142 when f8=> --8th falling edge
146 when r8=> --8th rising edge (adc gets PD0)
149 when f9=> --9th falling edge busy state between conversion (we write nothing)
152 when r9=> --9th rising edge (we nor ads get nothing)
155 when f10=> --10th falling edge
158 when r10=> --10th rising edge (we read 1. bit of conversion)
160 adc_data(11)<=adc_miso;
165 when r11=> --11th rising edge
167 adc_data(10)<=adc_miso;
172 when r12=> --12th rising edge
174 adc_data(9)<=adc_miso;
179 when r13=> --13th rising edge
181 adc_data(8)<=adc_miso;
186 when r14=> --14th rising edge
188 adc_data(7)<=adc_miso;
193 when r15=> --15th rising edge
195 adc_data(6)<=adc_miso;
196 if (reset_re='1') then --we check rising edge of reset