--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library std;
+use std.textio.all;
+
+--------------------------------------------------------------------------------
+
+entity priority_encoder is
+ generic (
+ SEL_W : integer := 16;
+ CODE_W : integer := 4);
+ port (
+ sel : in std_logic_vector (SEL_W-1 downto 0);
+ code : out std_logic_vector (CODE_W-1 downto 0));
+end entity priority_encoder;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of priority_encoder is
+
+--------------------------------------------------------------------------------
+
+begin
+
+ process (sel) is
+ begin
+ code <= (others => '-');
+
+ for i in 0 to SEL_W-1 loop
+ if sel(i) = '1' then
+ code <= conv_std_logic_vector(i, CODE_W);
+ end if;
+ end loop;
+ end process;
+
+end architecture behavioral;
+
-VHDL_MAIN = tb_vector_gen
+VHDL_MAIN = tb_priority_encoder
VHDL_ENTITIES = counter.o \
pwm.o \
wave_table.o \
- vector_gen.o
+ vector_gen.o \
+ priority_encoder.o
STOP_TIME = 50us
--- /dev/null
+[timestart] 0
+[size] 1280 746
+[pos] -279 -1
+*-33.327084 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+@28
+clk_i
+sel[3:0]
+code[1:0]
+[pattern_trace] 1
+[pattern_trace] 0
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity tb_priority_encoder is
+end tb_priority_encoder;
+
+--------------------------------------------------------------------------------
+
+architecture testbench of tb_priority_encoder is
+
+ constant period : time := 1 us;
+ constant offset : time := 0 us;
+
+ signal CLK_I : std_logic;
+ signal RST_I : std_logic;
+
+ signal SEL : std_logic_vector (3 downto 0);
+ signal CODE : std_logic_vector (1 downto 0);
+
+--------------------------------------------------------------------------------
+
+begin
+
+ uut: entity work.priority_encoder
+ generic map (
+ SEL_W => 4,
+ CODE_W => 2)
+ port map (
+ sel => SEL,
+ code => CODE);
+
+
+ SYSCON_CLK : process is
+ begin
+ CLK_I <= '0';
+ wait for offset;
+ loop
+ CLK_I <= '1';
+ wait for period/2;
+ CLK_I <= '0';
+ wait for period/2;
+ end loop;
+ end process;
+
+ SYSCON_RST : process is
+ begin
+ RST_I <= '0';
+ wait for offset;
+ wait for 0.75*period;
+ RST_I <= '1';
+ wait for 2*period;
+ RST_I <= '0';
+ wait;
+ end process;
+
+--------------------------------------------------------------------------------
+
+ UUT_FEED : process is
+ begin
+ SEL <= "0000";
+
+ wait for offset;
+ wait for 3*period;
+
+ for i in 1 to 15 loop
+ SEL <= conv_std_logic_vector(i, 4);
+ wait for 3*period;
+ end loop;
+
+ wait;
+ end process;
+
+end testbench;
+