Modified testbenches to use entities (not components)

diff --git a/tb/tb_pwm.vhd b/tb/tb_pwm.vhd
index 5dbaaca7aa3631534d428618d55066949535837c..3fed912c7dc32d22c671f826de9501ea9955bb24 100644 (file)
--- a/tb/tb_pwm.vhd
+++ b/tb/tb_pwm.vhd
@@ -26,37 +26,11 @@ architecture testbench of tb_pwm is
   signal pwm_cyc  : std_logic;
   signal pwm_out  : std_logic;
 
---------------------------------------------------------------------------------
-
-  component pwm is
-    generic (
-      PWM_WIDTH : integer);
-    port (
-      clk     : in  std_logic;
-      reset   : in  std_logic;
-      din     : in  std_logic_vector (PWM_WIDTH-1 downto 0);
-      we      : in  std_logic;
-      pwm_cnt : in  std_logic_vector (PWM_WIDTH-1 downto 0);
-      pwm_cyc : in  std_logic;
-      pwm     : out std_logic);
-  end component pwm;
-
-  component counter is
-    generic (
-      WIDTH : integer;
-      MAX   : integer);
-    port (
-      clk      : in  std_logic;
-      reset    : in  std_logic;
-      count    : out std_logic_vector (WIDTH-1 downto 0);
-      event_ow : out std_logic);
-  end component counter;
-  
 --------------------------------------------------------------------------------
   
 begin
 
-  uut : pwm
+  uut : entity work.pwm
     generic map (
       PWM_WIDTH => PWM_W)
     port map (
@@ -68,7 +42,7 @@ begin
       pwm_cyc => pwm_cyc,
       pwm     => pwm_out);
   
-  counter_1 : counter
+  counter_1 : entity work.counter
     generic map (
       WIDTH => PWM_W,
       MAX   => CNT_MAX)

diff --git a/tb/tb_vector_gen.vhd b/tb/tb_vector_gen.vhd
index 2de9ee0f0afc4bb09ad3c7ae2afe9a23019ebde7..1f66996674ad925f57a962311044036d556d744d 100644 (file)
--- a/tb/tb_vector_gen.vhd
+++ b/tb/tb_vector_gen.vhd
@@ -46,62 +46,11 @@ architecture testbench of tb_vector_gen is
   signal dbg_mem3 : word_t    := (others => '0');
   signal dbg_ack  : std_logic := '0';
 
---------------------------------------------------------------------------------
-
-  component vector_gen is
-    port (
-      ACK_O     : out std_logic;
-      CLK_I     : in  std_logic;
-      RST_I     : in  std_logic;
-      STB_I     : in  std_logic;
-      IRF_ACK_I : in  std_logic;
-      IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
-      IRF_CYC_O : out std_logic;
-      IRF_DAT_I : in  std_logic_vector (15 downto 0);
-      IRF_DAT_O : out std_logic_vector (15 downto 0);
-      IRF_STB_O : out std_logic;
-      IRF_WE_O  : out std_logic;
-      LUT_ADR_O : out std_logic_vector (LUT_ADR_W-1 downto 0);
-      LUT_DAT_I : in  std_logic_vector (LUT_DAT_W-1 downto 0);
-      LUT_STB_O : out std_logic);
-  end component vector_gen;
-  
-  component wave_table is
-    generic (
-      DAT_W     : integer;
-      ADR_W     : integer;
-      INIT_FILE : string);
-    port (
-      ACK_O : out std_logic;
-      ADR_I : in  std_logic_vector (ADR_W-1 downto 0);
-      CLK_I : in  std_logic;
-      DAT_I : in  std_logic_vector (DAT_W-1 downto 0);
-      DAT_O : out std_logic_vector (DAT_W-1 downto 0);
-      STB_I : in  std_logic;
-      WE_I  : in  std_logic);
-  end component wave_table;
-  
-  component test_mem is
-    generic (
-      DAT_W : integer;
-      ADR_W : integer);
-    port (
-      ACK_O : out std_logic;
-      ADR_I : in  std_logic_vector (ADR_W-1 downto 0);
-      CLK_I : in  std_logic;
-      DAT_I : in  std_logic_vector (DAT_W-1 downto 0);
-      DAT_O : out std_logic_vector (DAT_W-1 downto 0);
-      STB_I : in  std_logic;
-      WE_I  : in  std_logic);
-  end component test_mem;
-
-
-  
 --------------------------------------------------------------------------------
   
 begin
   
-  uut : vector_gen
+  uut : entity work.vector_gen
     port map (
       ACK_O     => ACK_O,
       CLK_I     => CLK_I,
@@ -118,7 +67,7 @@ begin
       LUT_DAT_I => LUT_DAT_I,
       LUT_STB_O => LUT_STB_O);
 
-  wave_table_1 : wave_table
+  wave_table_1 : entity work.wave_table
     generic map (
       DAT_W     => LUT_DAT_W,
       ADR_W     => LUT_ADR_W,

diff --git a/tb/tb_wave_table.vhd b/tb/tb_wave_table.vhd
index d0a8e29f7433cdc772154facd6568b623fc5dd47..f740641756fe06a6e9250f3484c97a04f3c35f63 100644 (file)
--- a/tb/tb_wave_table.vhd
+++ b/tb/tb_wave_table.vhd
@@ -29,28 +29,11 @@ architecture testbench of tb_wave_table is
   signal WE_I  : std_logic;
   signal RST_I : std_logic;
 
---------------------------------------------------------------------------------
-
-  component wave_table is
-    generic (
-      DAT_W     : integer;
-      ADR_W     : integer;
-      INIT_FILE : string);
-    port (
-      ACK_O : out std_logic;
-      ADR_I : in  std_logic_vector (ADR_W-1 downto 0);
-      CLK_I : in  std_logic;
-      DAT_I : in  std_logic_vector (DAT_W-1 downto 0);
-      DAT_O : out std_logic_vector (DAT_W-1 downto 0);
-      STB_I : in  std_logic;
-      WE_I  : in  std_logic);
-  end component wave_table;
-  
 --------------------------------------------------------------------------------
   
 begin
   
-  uut : wave_table
+  uut : entity work.wave_table
     generic map (
       DAT_W     => DAT_W,
       ADR_W     => ADR_W,