entity mcc is
generic (
LUT_ADR_W : integer := 10;
- LUT_DAT_W : integer := 9;
- IRF_ADR_W : integer := 5);
+ LUT_DAT_W : integer := 9);
port (
-- Primary slave intefrace
ACK_O : out std_logic;
architecture behavioral of mcc is
+ constant IRF_ADR_W : integer := 5;
+
constant MCC_W : integer := 6;
constant MUX_W : integer := 3;
constant LUT_DAT_W : integer := 10;
constant LUT_ADR_W : integer := 9;
constant LUT_INIT_FILE : string := "../sin.lut";
- constant IRF_ADR_W : integer := 5;
constant WAVE_SIZE : integer := 2**LUT_ADR_W;
signal STB_I : std_logic;
signal IRF_ACK_I : std_logic;
- signal IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+ signal IRF_ADR_O : std_logic_vector (4 downto 0);
signal IRF_CYC_O : std_logic;
signal IRF_DAT_I : std_logic_vector (15 downto 0);
signal IRF_DAT_O : std_logic_vector (15 downto 0);
uut : entity work.mcc
generic map (
LUT_ADR_W => LUT_ADR_W,
- LUT_DAT_W => LUT_DAT_W,
- IRF_ADR_W => IRF_ADR_W)
+ LUT_DAT_W => LUT_DAT_W)
port map (
ACK_O => ACK_O,
CLK_I => CLK_I,