Overflow event signal of counter corrected.

Signal is high only in a clock period, when counter is really overflowing.
It takes in clock enable signal.

diff --git a/counter.vhd b/counter.vhd
index 0994e811f7da1bfd78fe0e81e2f0b81f02560b31..9df0e2b86714c49dd95aa37bf1b3455f762e15cf 100644 (file)
--- a/counter.vhd
+++ b/counter.vhd
@@ -37,7 +37,7 @@ begin
 
   
   count    <= cnt;
-  event_ow <= eq_max;
+  event_ow <= eq_max and clk_en;
 
   
   COUTER : process (clk, reset) is