0x03 : IRC max
0x04 : Angle
0x05 : Action
-0x06 : reserved (Angle scale)
-0x07 : reserved (Scaled Angle)
-0x08 : reserved (Table base)
-0x09 : reserved (P2 offset)
-0x0A : reserved (P3 offset)
-0x0B : reserved (Table index mask)
-0x0C : reserved (PWM PID - P)
-0x0D : reserved (PWM PID - I)
-0x0E : reserved (PWM PID - D)
+0x06 : Min PWM
+0x07 : reserved (Angle scale)
+0x08 : reserved (Scaled Angle)
+0x09 : reserved (Table base)
+0x0A : reserved (P2 offset)
+0x0B : reserved (P3 offset)
+0x0C : reserved (Table index mask)
+0x0D : reserved (PWM PID - P)
+0x0E : reserved (PWM PID - I)
+0x0F : reserved (PWM PID - D)
// Phase 1
0x10 : Phase1
signal SCALE_SL_ACK_O : std_logic;
signal SCALE_SL_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
signal SCALE_SL_STB_I : std_logic;
+
+ signal PMIN_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+ signal PMIN_IRF_DAT_O : std_logic_vector (15 downto 0);
+ signal PMIN_IRF_STB_O : std_logic;
+ signal PMIN_IRF_WE_O : std_logic;
signal PWM_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
signal PWM_IRF_STB_O : std_logic;
BASE_IRF_ADR_O when MCC_MUX_CODE = 1 else
VECTOR_IRF_ADR_O when MCC_MUX_CODE = 2 else
SCALE_IRF_ADR_O when MCC_MUX_CODE = 3 else
+ PMIN_IRF_ADR_O when MCC_MUX_CODE = 4 else
PWM_IRF_ADR_O when MCC_MUX_CODE = 5 else
(others => 'X');
BASE_IRF_DAT_O when MCC_MUX_CODE = 1 else
VECTOR_IRF_DAT_O when MCC_MUX_CODE = 2 else
SCALE_IRF_DAT_O when MCC_MUX_CODE = 3 else
+ PMIN_IRF_DAT_O when MCC_MUX_CODE = 4 else
(others => 'X');
IRF_STB_O <= MASTER_IRF_STB_O when MCC_MUX_EN = '0' else
BASE_IRF_STB_O when MCC_MUX_CODE = 1 else
VECTOR_IRF_STB_O when MCC_MUX_CODE = 2 else
SCALE_IRF_STB_O when MCC_MUX_CODE = 3 else
+ PMIN_IRF_STB_O when MCC_MUX_CODE = 4 else
PWM_IRF_STB_O when MCC_MUX_CODE = 5 else
'0';
BASE_IRF_WE_O when MCC_MUX_CODE = 1 else
VECTOR_IRF_WE_O when MCC_MUX_CODE = 2 else
SCALE_IRF_WE_O when MCC_MUX_CODE = 3 else
+ PMIN_IRF_WE_O when MCC_MUX_CODE = 4 else
'0';
PWM2_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 1 else '0';
PWM3_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 2 else '0';
- MCC_ACK (4) <= '1';
mcc_master_1 : entity work.mcc_master
IRF_STB_O => SCALE_IRF_STB_O,
IRF_WE_O => SCALE_IRF_WE_O);
+ pwm_min_1 : entity work.pwm_min
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ PWM_W => LUT_DAT_W,
+ BASE => 0,
+ PWMMIN_OFF => 6,
+ P_BASE => P_BASE,
+ P_SIZE => P_SIZE,
+ PWM_OFF => 1)
+ port map (
+ ACK_O => MCC_ACK (4),
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => MCC_STB (4),
+ IRF_ACK_I => IRF_ACK_I,
+ IRF_ADR_O => PMIN_IRF_ADR_O,
+ IRF_DAT_I => IRF_DAT_I,
+ IRF_DAT_O => PMIN_IRF_DAT_O,
+ IRF_STB_O => PMIN_IRF_STB_O,
+ IRF_WE_O => PMIN_IRF_WE_O);
pwm_dump_sequencer : entity work.sequencer
generic map (
SL_STB_O => PWM_SL_STB_I,
SL_MUX_CODE => PWM_SL_MUX_CODE);
- pwm_dump_1 : entity work.pwm_dump
+ pwm_min_dump_1 : entity work.pwm_min_dump
generic map (
- IRF_ADR_W => IRF_ADR_W,
- P_BASE => P_BASE,
- PWM_OFF => 1,
- PWM_W => LUT_DAT_W)
+ IRF_ADR_W => IRF_ADR_W,
+ BASE => 0,
+ PWMMIN_OFF => 6,
+ P_BASE => P_BASE,
+ PWM_OFF => 1,
+ PWM_W => LUT_DAT_W)
port map (
ACK_O => PWM_SL_ACK_O,
CLK_I => CLK_I,