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(parent: 7c10fab) | patch
Overflow event signal of counter corrected.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Thu, 26 May 2011 20:39:07 +0000 (22:39 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Thu, 26 May 2011 20:39:07 +0000 (22:39 +0200)
commita10da24a32a673bbfdd80d12f73c1855d7721087
tree7aaa3bc41f7b06816d9597a49680b554af3f4428tree | snapshot
parent7c10fab4d2484fd07ed396ea5cd5407e48f90fb8commit | diff
Overflow event signal of counter corrected.

Signal is high only in a clock period, when counter is really overflowing.
It takes in clock enable signal.
counter.vhd diff | blob | history
The control block for three phases BLDC motor PWM output with profile based commutation logic