Early initialization of all relevant signals.

Initial states of all relevant signals were specified. Now it is not
required to do reset after start-up. Somewhere inititial states are
written in port declaration, but it would be better to move them
to architecture part.

diff --git a/counter.vhd b/counter.vhd
index 790d05485fbae44d9d2fa290e269f82242b73e99..3161c631b08b98a7f571b98698e2005d2aadd621 100644 (file)
--- a/counter.vhd
+++ b/counter.vhd
@@ -25,7 +25,7 @@ end counter;
 architecture behavioral of counter is
 
   signal eq_max : std_logic;            -- cnt is equal to MAX
-  signal cnt    : std_logic_vector (WIDTH-1 downto 0);
+  signal cnt    : std_logic_vector (WIDTH-1 downto 0) := (others => '0');
 
 --------------------------------------------------------------------------------
 

diff --git a/irc_base.vhd b/irc_base.vhd
index c99625a5d78a505418590926c9924feae8fcabd4..4af41937599d4384393f75ad84668abba543a2a9 100644 (file)
--- a/irc_base.vhd
+++ b/irc_base.vhd
@@ -15,7 +15,7 @@ entity irc_base is
     A_OFF     : integer := 4);
   port (
     -- Primary slave interface
-    ACK_O     : out std_logic;
+    ACK_O     : out std_logic := '0';
     CLK_I     : in  std_logic;
     RST_I     : in  std_logic;
     STB_I     : in  std_logic;
@@ -24,8 +24,8 @@ entity irc_base is
     IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
     IRF_DAT_I : in  std_logic_vector (15 downto 0);
     IRF_DAT_O : out std_logic_vector (15 downto 0);
-    IRF_STB_O : out std_logic;
-    IRF_WE_O  : out std_logic;
+    IRF_STB_O : out std_logic := '0';
+    IRF_WE_O  : out std_logic := '0';
     -- Error flag
     BAD_BASE : out std_logic);
 end entity irc_base;
@@ -43,7 +43,7 @@ architecture behavioral of irc_base is
   constant ANG_ADR  : irf_adr_t := conv_std_logic_vector(BASE+A_OFF, IRF_ADR_W);
 
   
-  signal state    : state_t;
+  signal state    : state_t := ready;
   signal irc      : std_logic_vector (15 downto 0);
   signal irc_base : std_logic_vector (15 downto 0);
   signal irc_per  : std_logic_vector (15 downto 0);

diff --git a/irc_dump.vhd b/irc_dump.vhd
index 3317b00d785d06ed7bc5521eaf92c3f42775279f..ee8b1b20465c17bcd03cd0b951c2baf1e8744043 100644 (file)
--- a/irc_dump.vhd
+++ b/irc_dump.vhd
@@ -33,7 +33,7 @@ architecture behavioral of irc_dump is
 
   constant IRC_ADR : irf_adr_t :=  conv_std_logic_vector(IRC_BASE, IRF_ADR_W);
   
-  signal INNER_ACK : std_logic;
+  signal INNER_ACK : std_logic := '0';
   
 --------------------------------------------------------------------------------
 

diff --git a/mcc_master.vhd b/mcc_master.vhd
index 12d5b943ec2d03c2d5a3757a248331ffe83347bc..0a09de8cad12a8c31323692b4b00388bc5920147 100644 (file)
--- a/mcc_master.vhd
+++ b/mcc_master.vhd
@@ -15,21 +15,21 @@ entity mcc_master is
     IRF_ADR_W : integer := 5);
   port (
     -- Primary slave intefrace
-    ACK_O        : out std_logic;
+    ACK_O        : out std_logic := '0';
     CLK_I        : in  std_logic;
     RST_I        : in  std_logic;
     STB_I        : in  std_logic;
     -- Motion Control Chain
-    MCC_STB_O    : out std_logic_vector (MCC_W-1 downto 0);
+    MCC_STB_O    : out std_logic_vector (MCC_W-1 downto 0) := (others => '0');
     MCC_ACK_I    : in  std_logic_vector (MCC_W-1 downto 0);
-    MCC_MUX_CODE : out std_logic_vector (MUX_W-1 downto 0);
-    MCC_MUX_EN   : out std_logic;
+    MCC_MUX_CODE : out std_logic_vector (MUX_W-1 downto 0) := (others => '0');
+    MCC_MUX_EN   : out std_logic := '0';
     -- Shared dual-port memory
     IRF_ACK_I    : in  std_logic;
     IRF_ADR_O    : out std_logic_vector (IRF_ADR_W-1 downto 0);
     IRF_DAT_I    : in  std_logic_vector (15 downto 0);
     IRF_DAT_O    : out std_logic_vector (15 downto 0);
-    IRF_STB_O    : out std_logic;
+    IRF_STB_O    : out std_logic := '0';
     IRF_WE_O     : out std_logic);
 end entity mcc_master;
 
@@ -39,13 +39,13 @@ architecture behavioral of mcc_master is
 
   type state_t is (ready, read_mask, do_mcc, done);
 
-  signal state : state_t;
+  signal state : state_t := ready;
 
   signal mcc_mask       : std_logic_vector (MCC_W-1 downto 0);
-  signal mcc_ack_inner  : std_logic_vector (MCC_W downto 0);
-  signal mcc_stb_inner  : std_logic_vector (MCC_W-1 downto 0);
+  signal mcc_ack_inner  : std_logic_vector (MCC_W downto 0) := (others => '0');
+  signal mcc_stb_inner  : std_logic_vector (MCC_W-1 downto 0) := (others => '0');
   signal mux_code_inner : std_logic_vector (MUX_W-1 downto 0);
-  signal mcc_exec       : std_logic;
+  signal mcc_exec       : std_logic := '0';
   
 --------------------------------------------------------------------------------
 

diff --git a/pwm.vhd b/pwm.vhd
index 4cfcc2906c4765d60697cb61a4b472cb4a910f03..3590d5423041628c317a966c69c3bf6069edae3d 100644 (file)
--- a/pwm.vhd
+++ b/pwm.vhd
@@ -42,9 +42,9 @@ end pwm;
 architecture behavioral of pwm is
 
   -- Register accessible from bus
-  signal reg : std_logic_vector (PWM_WIDTH-1 downto 0);
+  signal reg : std_logic_vector (PWM_WIDTH-1 downto 0) := (others => '0');
   -- Compare value during pwm cycle, loaded from 'reg' when new period begins.
-  signal cmp : std_logic_vector (PWM_WIDTH-1 downto 0);
+  signal cmp : std_logic_vector (PWM_WIDTH-1 downto 0) := (others => '0');
   
 --------------------------------------------------------------------------------
 

diff --git a/pwm_dump.vhd b/pwm_dump.vhd
index bf6b8c632bfd96b63ffa30e6be284013f3613494..8d942a1faa48618f8a7d32644950200a7455282f 100644 (file)
--- a/pwm_dump.vhd
+++ b/pwm_dump.vhd
@@ -19,7 +19,7 @@ entity pwm_dump is
     STB_I     : in  std_logic;
     -- PWM interface
     PWM_DAT_O : out std_logic_vector (PWM_W-1 downto 0);
-    PWM_STB_O : out std_logic;
+    PWM_STB_O : out std_logic := '0';
     -- Shared dual-port memory
     IRF_ACK_I : in  std_logic;
     IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
@@ -36,9 +36,9 @@ architecture behavioral of pwm_dump is
 
   constant PWM_ADR : irf_adr_t :=  conv_std_logic_vector(P_BASE + PWM_OFF, IRF_ADR_W);
   
-  signal state : state_t;
+  signal state : state_t := ready;
 
-  signal INNER_ACK : std_logic;
+  signal INNER_ACK : std_logic := '0';
   
 --------------------------------------------------------------------------------
 

diff --git a/sequencer.vhd b/sequencer.vhd
index 74733f8034ba0f66e164ebb43f441329e36896b4..59013e48051e20e1b9e984c8a1bca3064a10521d 100644 (file)
--- a/sequencer.vhd
+++ b/sequencer.vhd
@@ -21,7 +21,7 @@ entity sequencer is
     -- Slave interface
     SL_ACK_I     : in  std_logic;
     SL_IRF_ADR_I : in  std_logic_vector (IRF_ADR_W-1 downto 0);
-    SL_STB_O     : out std_logic;
+    SL_STB_O     : out std_logic := '0';
     SL_MUX_CODE  : out std_logic_vector (1 downto 0));
 end entity sequencer;
 
@@ -36,9 +36,9 @@ architecture behavioral of sequencer is
   constant P2_MASK: irf_adr_t := conv_std_logic_vector(P_BASE+1*P_SIZE, IRF_ADR_W);
   constant P3_MASK: irf_adr_t := conv_std_logic_vector(P_BASE+2*P_SIZE, IRF_ADR_W);
 
-  signal state     : state_t;
+  signal state     : state_t := ready;
 
-  signal INNER_ACK : std_logic;
+  signal INNER_ACK : std_logic := '0';
 
 --------------------------------------------------------------------------------
 

diff --git a/vector_gen.vhd b/vector_gen.vhd
index f32890bd4194ec9f3684893d958d4ba03bfbdda0..a58d255b3d0fb7f89dc95da512ec2c93274ff6ca 100644 (file)
--- a/vector_gen.vhd
+++ b/vector_gen.vhd
@@ -30,7 +30,7 @@ entity vector_gen is
     IRF_CYC_O : out std_logic;
     IRF_DAT_I : in  std_logic_vector (15 downto 0);
     IRF_DAT_O : out std_logic_vector (15 downto 0);
-    IRF_STB_O : out std_logic;
+    IRF_STB_O : out std_logic := '0';
     IRF_WE_O  : out std_logic;
     -- Master interface to the wave look-up-table
     LUT_ADR_O : out std_logic_vector (LUT_ADR_W-1 downto 0);
@@ -51,9 +51,9 @@ architecture behavioral of vector_gen is
   constant P2_ADR : irf_adr_t := conv_std_logic_vector(P_BASE+P2_OFF, IRF_ADR_W);
   constant P3_ADR : irf_adr_t := conv_std_logic_vector(P_BASE+P3_OFF, IRF_ADR_W);
 
-  signal state     : state_t;
+  signal state     : state_t := ready;
   signal angle_in  : lut_adr_t;
-  signal ack_latch : std_logic;
+  signal ack_latch : std_logic := '0';
 
 --------------------------------------------------------------------------------
   

diff --git a/vector_scale.vhd b/vector_scale.vhd
index 05fb7694a115736ad044470899122440db7435d9..d1c6306c34e731cf115cf379aeae805f03931e3e 100644 (file)
--- a/vector_scale.vhd
+++ b/vector_scale.vhd
@@ -29,8 +29,8 @@ entity vector_scale is
     IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
     IRF_DAT_I : in  std_logic_vector (15 downto 0);
     IRF_DAT_O : out std_logic_vector (15 downto 0);
-    IRF_STB_O : out std_logic;
-    IRF_WE_O  : out std_logic);
+    IRF_STB_O : out std_logic := '0';
+    IRF_WE_O  : out std_logic := '0');
 end entity vector_scale;
 
 --------------------------------------------------------------------------------
@@ -46,9 +46,9 @@ architecture behavioral of vector_scale is
   constant VECTOR_ADR : irf_adr_t := conv_std_logic_vector(PHASE_BASE + VECTOR_OFF, IRF_ADR_W);
   constant SCALED_ADR : irf_adr_t := conv_std_logic_vector(PHASE_BASE + SCALED_OFF, IRF_ADR_W);
   
-  signal state : state_t;
+  signal state : state_t := ready;
 
-  signal INNER_ACK : std_logic;
+  signal INNER_ACK : std_logic := '0';
 
 
   function twos_to_biased (twos : std_logic_vector) return std_logic_vector is