rtime.felk.cvut.cz Git - fpga/pwm.git/commit

]> rtime.felk.cvut.cz Git - fpga/pwm.git/commit

author	Vladimir Burian <buriavl2@fel.cvut.cz>
	Wed, 18 May 2011 19:32:23 +0000 (21:32 +0200)
committer	Vladimir Burian <buriavl2@fel.cvut.cz>
	Wed, 18 May 2011 20:10:19 +0000 (22:10 +0200)
commit	899c4aaf8411af38d4077fd70ef8872e5093b6f0
tree	3cb8d9ab9f3f9b6c37476386a46608d78b08287a	tree \| snapshot
parent	2ab0234f25bea3d2466c9e8179b94f6d515cff8b	commit \| diff

Early initialization of all relevant signals.

Initial states of all relevant signals were specified. Now it is not
required to do reset after start-up. Somewhere inititial states are
written in port declaration, but it would be better to move them
to architecture part.

counter.vhd		diff \| blob \| history
irc_base.vhd		diff \| blob \| history
irc_dump.vhd		diff \| blob \| history
mcc_master.vhd		diff \| blob \| history
pwm.vhd		diff \| blob \| history
pwm_dump.vhd		diff \| blob \| history
sequencer.vhd		diff \| blob \| history
vector_gen.vhd		diff \| blob \| history
vector_scale.vhd		diff \| blob \| history

The control block for three phases BLDC motor PWM output with profile based commutation logic

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