]> rtime.felk.cvut.cz Git - fpga/pwm.git/blob - tb/Makefile
Changed testbench Makefile.
[fpga/pwm.git] / tb / Makefile
1 VHDL_MAIN     = tb_vector_gen
2 VHDL_ENTITIES = counter.o \
3                 pwm.o \
4                 wave_table.o \
5                 vector_gen.o
6
7 STOP_TIME     = 50us
8
9
10 all: $(VHDL_MAIN)
11
12 run: $(VHDL_MAIN)
13         ghdl -r $< --stop-time=$(STOP_TIME) --vcd=$<.vcd
14
15 view: run
16         gtkwave $(VHDL_MAIN).vcd $(VHDL_MAIN).sav
17
18 $(VHDL_MAIN): $(VHDL_ENTITIES) $(VHDL_MAIN).o
19         ghdl -e -fexplicit --ieee=synopsys $@
20
21 %.o: %.vhd
22         ghdl -a -fexplicit --ieee=synopsys $<
23
24 %.o: ../%.vhd
25         ghdl -a -fexplicit --ieee=synopsys $<
26
27 clean:
28         rm -Rf *.o *.vcd $(VHDL_MAIN) results.txt work-obj93.cf
29