]> rtime.felk.cvut.cz Git - fpga/pwm.git/commitdiff
Changed testbench Makefile.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Sun, 20 Mar 2011 18:16:54 +0000 (19:16 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Sun, 20 Mar 2011 18:25:40 +0000 (19:25 +0100)
It's now possible to work with "work" library and directly instantiate
entities (not components).

tb/Makefile

index b77d80407bd13aadb6f6616eec14d4dc0adeced7..8516090181073f193c01c549ecc3282938be1b1b 100644 (file)
@@ -15,7 +15,7 @@ run: $(VHDL_MAIN)
 view: run
        gtkwave $(VHDL_MAIN).vcd $(VHDL_MAIN).sav
 
-$(VHDL_MAIN): $(VHDL_MAIN).o $(VHDL_ENTITIES)
+$(VHDL_MAIN): $(VHDL_ENTITIES) $(VHDL_MAIN).o
        ghdl -e -fexplicit --ieee=synopsys $@
 
 %.o: %.vhd