]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-rocon.git/history - hw/lxmaster_transmitter.vhd
Add registers to LX Master MOSI and SYNC signals to ensure right timing.
[fpga/lx-cpu1/lx-rocon.git] / hw / lxmaster_transmitter.vhd
2014-12-06 Pavel PisaAdd registers to LX Master MOSI and SYNC signals to...
2014-11-23 Pavel PisaMade LX Master communication frame configurable.
2014-06-09 Martin MelounUpdate FPGA, fix hazard conditions in BRAM
2014-06-02 Pavel PisaMerge branch 'master' of rtime.felk.cvut.cz:/fpga/lx...
2014-06-02 Martin MelounUpdate dff2, create dff3, fix LX Master for multiple...
2014-05-30 Martin MelounLX Master watchdog implemented
2014-05-30 Martin MelounFix LX Master transmission, update PXMC for new structure
2014-05-30 Martin MelounUpdate LX Master transmitter structure layout
2014-05-30 Martin MelounUpdate LX PWR communication
2014-05-27 Pavel PisaMerge 8x IRC support from origin/master branch into...
2014-05-27 Martin MelounSupport 8 IRCs, refactorization (IRC and LXMaster regis...