Add registers to LX Master MOSI and SYNC signals to ensure right timing.

Changed location to falling clock phase to adjust timing.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/hw/lxmaster_transmitter.vhd b/hw/lxmaster_transmitter.vhd
index cb178a8c9d1561f0077fae33d43743328d67edb4..1c9153c310cdd74eebed0044408464c0cd7b644d 100644 (file)
--- a/hw/lxmaster_transmitter.vhd
+++ b/hw/lxmaster_transmitter.vhd
@@ -88,15 +88,23 @@ architecture Behavioral of lxmaster_transmitter is
        -- Bit 1: Watchdog not kicked (O)
        signal lxmaster_register_in_s   : std_logic;
        signal lxmaster_register_out_s  : std_logic_vector(1 downto 0);
+       -- Output buffers
+       signal sync_s                   : std_logic;
+       signal sync_r                   : std_logic;
+       signal mosi_s                   : std_logic;
+       signal mosi_r                   : std_logic;
 
 begin
 
        -- Directly route out some signals
        clock_o              <= clk_i; -- Cannot mix with logic
-       sync_o               <= not lxmaster_sync_r; -- Active in log. 0
-       mosi_o               <= '1' when lxmaster_sync_r = '0' and lxmaster_sync_last_bit_r = '0'
+       sync_s               <= not lxmaster_sync_r; -- Active in log. 0
+       mosi_s               <= '1' when lxmaster_sync_r = '0' and lxmaster_sync_last_bit_r = '0'
                                 else lxmaster_crc_reg_r(0) when lxmaster_state_r = ST_CRC
                                 else lxmaster_loaded_data_r(0);
+       sync_o               <= sync_r;
+       mosi_o               <= mosi_r;
+
        -- CRC
        lxmaster_crc_reg_s   <= '0' & lxmaster_crc_reg_r(7 downto 1) when lxmaster_state_r = ST_CRC else lxmaster_crc_out_s;
        lxmaster_crc_data_s  <= '1' when lxmaster_state_r = ST_CRC else lxmaster_loaded_data_r(0);
@@ -369,4 +377,13 @@ state:
 
        end process;
 
+update_outputs:
+       process
+       begin
+               wait until clk_i'event and clk_i = '0';
+
+               sync_r  <= sync_s;
+               mosi_r  <= mosi_s;
+       end process;
+
 end Behavioral;