]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-rocon.git/commit
Add registers to LX Master MOSI and SYNC signals to ensure right timing.
authorPavel Pisa <ppisa@pikron.com>
Sat, 6 Dec 2014 23:36:28 +0000 (00:36 +0100)
committerPavel Pisa <ppisa@pikron.com>
Sat, 6 Dec 2014 23:36:28 +0000 (00:36 +0100)
commitca2d6f4e7cce1d41a8415f70b7f2291d45678f56
tree60665228c57d22a841dca5e84e945a480fe4d801
parent4f3af62b15f1a5a458878fce1c02b9e6d629fb3d
Add registers to LX Master MOSI and SYNC signals to ensure right timing.

Changed location to falling clock phase to adjust timing.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
hw/lxmaster_transmitter.vhd