port
(
-- Clock
- clk : in std_logic;
-
+ clk_i : in std_logic;
-- Reset
- reset : in std_logic;
-
+ reset_i : in std_logic;
-- Chip enable
- ce : in std_logic;
-
+ ce_i : in std_logic;
-- Address
- address : in std_logic_vector(1 downto 0);
-
+ address_i : in std_logic_vector(1 downto 0);
-- Data bus
- data_in : in std_logic_vector(31 downto 0);
- data_out : out std_logic_vector(31 downto 0);
-
+ data_i : in std_logic_vector(31 downto 0);
+ data_o : out std_logic_vector(31 downto 0);
-- Bus signals
- rd : in std_logic;
- bls : in std_logic_vector(3 downto 0);
- ta : out std_logic
+ rd_i : in std_logic;
+ bls_i : in std_logic_vector(3 downto 0);
+ ta_o : out std_logic
);
end bus_calibration;
architecture Behavioral of bus_calibration is
-- Wiring
- signal read1_out : std_logic_vector(31 downto 0);
- signal read1_ta : std_logic;
+ signal read1_out_s : std_logic_vector(31 downto 0);
+ signal read1_ta_s : std_logic;
- signal read2_out : std_logic_vector(31 downto 0);
- signal read2_ta : std_logic;
+ signal read2_out_s : std_logic_vector(31 downto 0);
+ signal read2_ta_s : std_logic;
- signal write1_out : std_logic_vector(31 downto 0);
- signal write1_ta : std_logic;
- signal write1_ce : std_logic;
+ signal write1_out_s : std_logic_vector(31 downto 0);
+ signal write1_ta_s : std_logic;
+ signal write1_ce_s : std_logic;
- signal write2_out : std_logic_vector(31 downto 0);
- signal write2_ta : std_logic;
- signal write2_ce : std_logic;
+ signal write2_out_s : std_logic_vector(31 downto 0);
+ signal write2_ta_s : std_logic;
+ signal write2_ce_s : std_logic;
begin
memory_bus_calib_read1: calibration_read_register
generic map
(
- id => "10101010101010101010101010101010"
+ id_g => "10101010101010101010101010101010"
)
port map
(
- rd => rd,
- ta => read1_ta,
- data_out => read1_out
+ rd_i => rd_i,
+ ta_o => read1_ta_s,
+ data_o => read1_out_s
);
-- Second read calibration register (=0x55555555)
memory_bus_calib_read2: calibration_read_register
generic map
(
- id => "01010101010101010101010101010101"
+ id_g => "01010101010101010101010101010101"
)
port map
(
- rd => rd,
- ta => read2_ta,
- data_out => read2_out
+ rd_i => rd_i,
+ ta_o => read2_ta_s,
+ data_o => read2_out_s
);
-- First write calibration register
memory_bus_calib_write1: calibration_write_register
port map
(
- clk => clk,
- ce => write1_ce,
- reset => reset,
- rd => rd,
- bls => bls,
- ta => write1_ta,
- data_in => data_in,
- data_out => write1_out
+ clk_i => clk_i,
+ ce_i => write1_ce_s,
+ reset_i => reset_i,
+ rd_i => rd_i,
+ bls_i => bls_i,
+ ta_o => write1_ta_s,
+ data_i => data_i,
+ data_o => write1_out_s
);
-- Second write calibration register
memory_bus_calib_write2: calibration_write_register
port map
(
- clk => clk,
- ce => write2_ce,
- reset => reset,
- rd => rd,
- bls => bls,
- ta => write2_ta,
- data_in => data_in,
- data_out => write2_out
+ clk_i => clk_i,
+ ce_i => write2_ce_s,
+ reset_i => reset_i,
+ rd_i => rd_i,
+ bls_i => bls_i,
+ ta_o => write2_ta_s,
+ data_i => data_i,
+ data_o => write2_out_s
);
-- Processes
- update: process (clk)
+update:
+ process (clk_i)
begin
- if clk = '1' and clk'event then
+ if clk_i = '1' and clk_i'event then
-- Defaults
- write1_ce <= '1';
- write2_ce <= '1';
-
- ta <= '1';
- data_out <= (others => 'X');
+ write1_ce_s <= '0';
+ write2_ce_s <= '0';
+ ta_o <= '0';
+ data_o <= (others => 'X');
-- Chip Enable
-- This will delay the register read / write
- if ce = '0' then
- case address is
- when "00" => -- Read1
- ta <= read1_ta;
- data_out <= read1_out;
- when "01" => -- Read2
- ta <= read2_ta;
- data_out <= read2_out;
+ if ce_i = '1' then
+ case address_i is
+ when "00" => -- Read1
+ ta_o <= read1_ta_s;
+ data_o <= read1_out_s;
+ when "01" => -- Read2
+ ta_o <= read2_ta_s;
+ data_o <= read2_out_s;
when "10" => -- Write1
- write1_ce <= '0';
- ta <= write1_ta;
- data_out <= write1_out;
- when "11" => -- Write2
- write2_ce <= '0';
- ta <= write2_ta;
- data_out <= write2_out;
+ write1_ce_s <= '1';
+ ta_o <= write1_ta_s;
+ data_o <= write1_out_s;
+ when "11" => -- Write2
+ write2_ce_s <= '1';
+ ta_o <= write2_ta_s;
+ data_o <= write2_out_s;
when others =>
- ta <= '1';
- data_out <= (others => 'X');
+ null;
end case;
end if;
entity bus_irc is
port
(
- clk : in std_logic;
- reset : in std_logic;
-
+ clk_i : in std_logic;
+ reset_i : in std_logic;
-- Address (needs just last 4 bits, rest is wired to CE)
- address : in std_logic_vector(3 downto 0);
- ce : in std_logic;
-
+ address_i : in std_logic_vector(3 downto 0);
+ ce_i : in std_logic;
-- Data bus
- data_in : in std_logic; -- 1 bit input
- data_out : out std_logic_vector(31 downto 0);
-
+ data_i : in std_logic; -- 1 bit input
+ data_o : out std_logic_vector(31 downto 0);
-- Bus signals
- rd : in std_logic;
- ta : out std_logic;
- wr : in std_logic;
-
+ rd_i : in std_logic;
+ ta_o : out std_logic;
+ wr_i : in std_logic;
-- Signals for IRC
- irc1_a : in std_logic;
- irc1_b : in std_logic;
- irc1_index : in std_logic;
- irc1_mark : in std_logic;
-
- irc2_a : in std_logic;
- irc2_b : in std_logic;
- irc2_index : in std_logic;
- irc2_mark : in std_logic;
-
- irc3_a : in std_logic;
- irc3_b : in std_logic;
- irc3_index : in std_logic;
- irc3_mark : in std_logic;
-
- irc4_a : in std_logic;
- irc4_b : in std_logic;
- irc4_index : in std_logic;
- irc4_mark : in std_logic
-
+ irc1_a_i : in std_logic;
+ irc1_b_i : in std_logic;
+ irc1_index_i : in std_logic;
+ irc1_mark_i : in std_logic;
+ --
+ irc2_a_i : in std_logic;
+ irc2_b_i : in std_logic;
+ irc2_index_i : in std_logic;
+ irc2_mark_i : in std_logic;
+ --
+ irc3_a_i : in std_logic;
+ irc3_b_i : in std_logic;
+ irc3_index_i : in std_logic;
+ irc3_mark_i : in std_logic;
+ --
+ irc4_a_i : in std_logic;
+ irc4_b_i : in std_logic;
+ irc4_index_i : in std_logic;
+ irc4_mark_i : in std_logic
);
end bus_irc;
architecture Behavioral of bus_irc is
-- Multiplexer signals
- signal irc1_out : std_logic_vector(31 downto 0);
- signal irc1_ta : std_logic;
- signal irc1_ce : std_logic_vector(1 downto 0);
+ signal irc1_out_s : std_logic_vector(31 downto 0);
+ signal irc1_ta_s : std_logic;
+ signal irc1_ce_s : std_logic_vector(1 downto 0);
- signal irc2_out : std_logic_vector(31 downto 0);
- signal irc2_ta : std_logic;
- signal irc2_ce : std_logic_vector(1 downto 0);
+ signal irc2_out_s : std_logic_vector(31 downto 0);
+ signal irc2_ta_s : std_logic;
+ signal irc2_ce_s : std_logic_vector(1 downto 0);
- signal irc3_out : std_logic_vector(31 downto 0);
- signal irc3_ta : std_logic;
- signal irc3_ce : std_logic_vector(1 downto 0);
+ signal irc3_out_s : std_logic_vector(31 downto 0);
+ signal irc3_ta_s : std_logic;
+ signal irc3_ce_s : std_logic_vector(1 downto 0);
- signal irc4_out : std_logic_vector(31 downto 0);
- signal irc4_ta : std_logic;
- signal irc4_ce : std_logic_vector(1 downto 0);
+ signal irc4_out_s : std_logic_vector(31 downto 0);
+ signal irc4_ta_s : std_logic;
+ signal irc4_ce_s : std_logic_vector(1 downto 0);
begin
irc1: irc_register
port map
(
- clk => clk,
- reset => reset,
- a0 => irc1_a,
- b0 => irc1_b,
- index0 => irc1_index,
- mark0 => irc1_mark,
- data_in => data_in,
- data_out => irc1_out,
- ce => irc1_ce,
- rd => rd,
- ta => irc1_ta,
- wr => wr
+ clk_i => clk_i,
+ reset_i => reset_i,
+ a0_i => irc1_a_i,
+ b0_i => irc1_b_i,
+ index0_i => irc1_index_i,
+ mark0_i => irc1_mark_i,
+ data_i => data_i,
+ data_o => irc1_out_s,
+ ce_i => irc1_ce_s,
+ rd_i => rd_i,
+ ta_o => irc1_ta_s,
+ wr_i => wr_i
);
-- IRC for second axis
irc2: irc_register
port map
(
- clk => clk,
- reset => reset,
- a0 => irc2_a,
- b0 => irc2_b,
- index0 => irc2_index,
- mark0 => irc2_mark,
- data_in => data_in,
- data_out => irc2_out,
- ce => irc2_ce,
- rd => rd,
- ta => irc2_ta,
- wr => wr
+ clk_i => clk_i,
+ reset_i => reset_i,
+ a0_i => irc2_a_i,
+ b0_i => irc2_b_i,
+ index0_i => irc2_index_i,
+ mark0_i => irc2_mark_i,
+ data_i => data_i,
+ data_o => irc2_out_s,
+ ce_i => irc2_ce_s,
+ rd_i => rd_i,
+ ta_o => irc2_ta_s,
+ wr_i => wr_i
);
-- IRC for thrid axis
irc3: irc_register
port map
(
- clk => clk,
- reset => reset,
- a0 => irc3_a,
- b0 => irc3_b,
- index0 => irc3_index,
- mark0 => irc3_mark,
- data_in => data_in,
- data_out => irc3_out,
- ce => irc3_ce,
- rd => rd,
- ta => irc3_ta,
- wr => wr
+ clk_i => clk_i,
+ reset_i => reset_i,
+ a0_i => irc3_a_i,
+ b0_i => irc3_b_i,
+ index0_i => irc3_index_i,
+ mark0_i => irc3_mark_i,
+ data_i => data_i,
+ data_o => irc3_out_s,
+ ce_i => irc3_ce_s,
+ rd_i => rd_i,
+ ta_o => irc3_ta_s,
+ wr_i => wr_i
);
-- IRC for fourth axis
irc4: irc_register
port map
(
- clk => clk,
- reset => reset,
- a0 => irc4_a,
- b0 => irc4_b,
- index0 => irc4_index,
- mark0 => irc4_mark,
- data_in => data_in,
- data_out => irc4_out,
- ce => irc4_ce,
- rd => rd,
- ta => irc4_ta,
- wr => wr
+ clk_i => clk_i,
+ reset_i => reset_i,
+ a0_i => irc4_a_i,
+ b0_i => irc4_b_i,
+ index0_i => irc4_index_i,
+ mark0_i => irc4_mark_i,
+ data_i => data_i,
+ data_o => irc4_out_s,
+ ce_i => irc4_ce_s,
+ rd_i => rd_i,
+ ta_o => irc4_ta_s,
+ wr_i => wr_i
);
-- Bus update
- memory_bus_update: process(ce, address, irc1_out, irc1_ta, irc2_out, irc2_ta,
- irc3_out, irc3_ta, irc4_out, irc4_ta)
+ memory_bus_update: process(ce_i, address_i, irc1_out_s, irc1_ta_s, irc2_out_s, irc2_ta_s,
+ irc3_out_s, irc3_ta_s, irc4_out_s, irc4_ta_s)
begin
-- Reset signals
- irc1_ce <= "11";
- irc2_ce <= "11";
- irc3_ce <= "11";
- irc4_ce <= "11";
+ -- 11 is the inactive address here
+ irc1_ce_s <= "11";
+ irc2_ce_s <= "11";
+ irc3_ce_s <= "11";
+ irc4_ce_s <= "11";
- ta <= '1';
- data_out <= (others => 'X');
+ ta_o <= '0';
+ data_o <= (others => 'X');
- if ce = '0' then
+ if ce_i = '1' then
-- We have 4-bit address, and IRC module has 3 registers
-- Higher bits choose which IRC module, lower bits are for registers of the module
- case address(3 downto 2) is
+ case address_i(3 downto 2) is
when "00" =>
- irc1_ce <= address(1 downto 0);
- data_out <= irc1_out;
- ta <= irc1_ta;
+ irc1_ce_s <= address_i(1 downto 0);
+ data_o <= irc1_out_s;
+ ta_o <= irc1_ta_s;
when "01" =>
- irc2_ce <= address(1 downto 0);
- data_out <= irc2_out;
- ta <= irc2_ta;
+ irc2_ce_s <= address_i(1 downto 0);
+ data_o <= irc2_out_s;
+ ta_o <= irc2_ta_s;
when "10" =>
- irc3_ce <= address(1 downto 0);
- data_out <= irc3_out;
- ta <= irc3_ta;
+ irc3_ce_s <= address_i(1 downto 0);
+ data_o <= irc3_out_s;
+ ta_o <= irc3_ta_s;
when "11" =>
- irc4_ce <= address(1 downto 0);
- data_out <= irc4_out;
- ta <= irc4_ta;
+ irc4_ce_s <= address_i(1 downto 0);
+ data_o <= irc4_out_s;
+ ta_o <= irc4_ta_s;
- when others => NULL;
+ when others =>
+ NULL;
end case;
-
end if;
end process;
end Behavioral;
-
port
(
-- Clock
- clk_100m : in std_logic;
- clk_50m : in std_logic;
-
+ clk_100m_i : in std_logic;
+ clk_50m_i : in std_logic;
-- Chip enable
- ce : in std_logic;
-
+ ce_100m_i : in std_logic;
-- Global Reset
- reset : in std_logic;
-
+ reset_100m_i : in std_logic;
-- Master CPU bus for the memory
- rd : in std_logic;
- bls : in std_logic_vector(3 downto 0);
- address : in std_logic_vector(11 downto 0);
- data_in : in std_logic_vector(31 downto 0);
- data_out : out std_logic_vector(31 downto 0);
- ta : out std_logic;
-
+ rd_100m_i : in std_logic;
+ bls_100m_i : in std_logic_vector(3 downto 0);
+ address_100m_i : in std_logic_vector(11 downto 0);
+ data_100m_i : in std_logic_vector(31 downto 0);
+ data_100m_o : out std_logic_vector(31 downto 0);
+ ta_100m_o : out std_logic;
-- Tumbl extrenal memory bus
- XMEMB_sel_o : out std_logic;
- XMEMB_i : in DMEMB2CORE_Type;
- XMEMB_o : out CORE2DMEMB_Type
+ XMEMB_sel_50m_o : out std_logic;
+ XMEMB_50m_i : in DMEMB2CORE_Type;
+ XMEMB_50m_o : out CORE2DMEMB_Type
);
end bus_tumbl;
architecture Behavioral of bus_tumbl is
-- Internal state
- signal tumbl_reset : std_logic;
- signal tumbl_halt : std_logic;
- signal tumbl_int : std_logic;
- signal tumbl_trace : std_logic;
- signal tumbl_trace_kick : std_logic; -- driven by 50M clock
- signal tumbl_trace_kick_ack : std_logic; -- driven by 50M clock
- signal tumbl_trace_kick_req : std_logic; -- driven by 100M clock
- signal tumbl_bad_op : std_logic; -- driven by 50M clock
+ -- The following signals are driven by 100M clock
+ signal tumbl_reset_100m_s : std_logic;
+ signal tumbl_halt_100m_s : std_logic;
+ signal tumbl_int_100m_s : std_logic;
+ signal tumbl_trace_100m_s : std_logic;
+
+ -- The following signals kick in at 50M clock
+ signal tumbl_reset_50m_s : std_logic;
+ signal tumbl_halt_50m_s : std_logic;
+ signal tumbl_int_50m_s : std_logic;
+ signal tumbl_trace_50m_s : std_logic;
+
+ -- Trace kick (since this is "one cycle command", it needs req / ack)
+ signal tumbl_trace_kick_50m_s : std_logic;
+ signal tumbl_trace_kick_ack_50m_s : std_logic;
+ signal tumbl_trace_kick_req_100m_s : std_logic;
-- Tumbl PC (copy it with cpu clock and then wire further)
- signal tumbl_pc : std_logic_vector(31 downto 0); -- driven by 50M clock
+ signal tumbl_pc_50m_s : std_logic_vector(31 downto 0);
-- Halting using halt instruction
- signal tumbl_halted : std_logic;
- signal tumbl_halt_code : std_logic_vector(4 downto 0);
+ -- Driven by 50M clock
+ signal tumbl_halted_50m_s : std_logic;
+ signal tumbl_halt_code_50m_s : std_logic_vector(4 downto 0);
+
+ -- Tumbl signals under 100M domain
+ -- Driven by 100M clock
+ -- TODO: Maybe filtered? It still may happen to read them when switching
+ -- despite the 2x clock when going from faster to slower domain.
+ signal tumbl_pc_100m_s : std_logic_vector(31 downto 0);
+ signal tumbl_halted_100m_s : std_logic;
+ signal tumbl_halt_code_100m_s : std_logic_vector(4 downto 0);
-- Internal memory signals
- signal imem_en : std_logic;
- signal dmem_en : std_logic;
+ -- Driven by 100M clock
+ signal imem_en_100m_s : std_logic;
+ signal dmem_en_100m_s : std_logic;
- signal imem_we : std_logic_vector(3 downto 0);
- signal dmem_we : std_logic_vector(3 downto 0);
+ signal imem_we_100m_s : std_logic_vector(3 downto 0);
+ signal dmem_we_100m_s : std_logic_vector(3 downto 0);
- signal imem_dout : std_logic_vector(31 downto 0);
- signal dmem_dout : std_logic_vector(31 downto 0);
+ signal imem_data_o_100m_s : std_logic_vector(31 downto 0);
+ signal dmem_data_o_100m_s : std_logic_vector(31 downto 0);
-- Internal bus structure
-- 12 address bits: 2 bits for selection, 10 bits for address
-- Registers
-- 0x000
--
- -- Bit 0: R/W - Reset
- -- Bit 1: R/W - Interrupt
- -- Bit 2: R/W - Halt
- -- Bit 3: R/W - Trace
- -- Bit 4: R - Halted
- -- Bit 5: R - Done
- -- Bit 6: R - Bad Op (halts the core until reset)
+ -- Bit 0: RW - Reset
+ -- Bit 1: RW - Interrupt
+ -- Bit 2: RW - Halt
+ -- Bit 3: RW - Trace
+ -- Bit 4: R - Halted
-- 0x001
- -- Bit 0: W - Write 1 for trace kick, R - Read internal signals
+ -- Bit 0: W - Write 1 for trace kick
-- 0x002
-- Tumbl program counter (R)
)
port map
(
- clk_i => clk_50m,
- rst_i => tumbl_reset,
- halt_i => tumbl_halt,
- int_i => tumbl_int,
- trace_i => tumbl_trace,
- trace_kick_i => tumbl_trace_kick,
+ clk_i => clk_50m_i,
+ rst_i => tumbl_reset_50m_s,
+ halt_i => tumbl_halt_50m_s,
+ int_i => tumbl_int_50m_s,
+ trace_i => tumbl_trace_50m_s,
+ trace_kick_i => tumbl_trace_kick_50m_s,
- pc_o => tumbl_pc,
- halted_o => tumbl_halted,
- halt_code_o => tumbl_halt_code,
+ pc_o => tumbl_pc_50m_s,
+ halted_o => tumbl_halted_50m_s,
+ halt_code_o => tumbl_halt_code_50m_s,
-- Internal memory (instruction)
- imem_clk => clk_100m,
- imem_en => imem_en,
- imem_we => imem_we,
- imem_addr => address(8 downto 0),
- imem_din => data_in,
- imem_dout => imem_dout,
+ imem_clk_i => clk_100m_i,
+ imem_en_i => imem_en_100m_s,
+ imem_we_i => imem_we_100m_s,
+ imem_addr_i => address_100m_i(8 downto 0),
+ imem_data_i => data_100m_i,
+ imem_data_o => imem_data_o_100m_s,
-- Internal memory (data)
- dmem_clk => clk_100m,
- dmem_en => dmem_en,
- dmem_we => dmem_we,
- dmem_addr => address(9 downto 0),
- dmem_din => data_in,
- dmem_dout => dmem_dout,
+ dmem_clk_i => clk_100m_i,
+ dmem_en_i => dmem_en_100m_s,
+ dmem_we_i => dmem_we_100m_s,
+ dmem_addr_i => address_100m_i(9 downto 0),
+ dmem_data_i => data_100m_i,
+ dmem_data_o => dmem_data_o_100m_s,
-- External memory bus
- XMEMB_sel_o => XMEMB_sel_o,
- XMEMB_i => XMEMB_i,
- XMEMB_o => XMEMB_o,
- --
- bad_op_o => tumbl_bad_op
+ XMEMB_sel_o => XMEMB_sel_50m_o,
+ XMEMB_i => XMEMB_50m_i,
+ XMEMB_o => XMEMB_50m_o
);
-- Enabling
- enabling: process(ce, address)
+ enabling: process(ce_100m_i, address_100m_i)
begin
- if ce = '0' and address(11 downto 10) = "00" then
- imem_en <= '1';
+ if ce_100m_i = '1' and address_100m_i(11 downto 10) = "00" then
+ imem_en_100m_s <= '1';
else
- imem_en <= '0';
+ imem_en_100m_s <= '0';
end if;
- if ce = '0' and address(11 downto 10) = "01" then
- dmem_en <= '1';
+ if ce_100m_i = '1' and address_100m_i(11 downto 10) = "01" then
+ dmem_en_100m_s <= '1';
else
- dmem_en <= '0';
+ dmem_en_100m_s <= '0';
end if;
end process;
-- Wiring
- wiring: process(ce, rd, bls, address, imem_en, imem_dout, dmem_en, dmem_dout,
- tumbl_reset, tumbl_int, tumbl_halt, tumbl_trace,
- tumbl_halted, tumbl_halt_code, tumbl_bad_op, tumbl_pc)
+ -- NOTE: This is only modifying signals inside 100m domain
+ wiring: process(ce_100m_i, rd_100m_i, bls_100m_i, address_100m_i, imem_en_100m_s, imem_data_o_100m_s, dmem_en_100m_s,
+ dmem_data_o_100m_s, tumbl_reset_100m_s, tumbl_int_100m_s, tumbl_halt_100m_s, tumbl_trace_100m_s,
+ tumbl_halted_100m_s, tumbl_halt_code_100m_s, tumbl_pc_100m_s)
begin
- if imem_en = '1' and tumbl_reset = '1' then
- imem_we <= not bls;
+ if imem_en_100m_s = '1' then
+ imem_we_100m_s <= bls_100m_i;
else
- imem_we <= "0000";
+ imem_we_100m_s <= "0000";
end if;
- if dmem_en = '1' and tumbl_reset = '1' then
- dmem_we <= not bls;
+ if dmem_en_100m_s = '1' then
+ dmem_we_100m_s <= bls_100m_i;
else
- dmem_we <= "0000";
+ dmem_we_100m_s <= "0000";
end if;
- if imem_en = '1' then
- data_out <= imem_dout;
- elsif dmem_en = '1' then
- data_out <= dmem_dout;
- elsif ce = '0' and rd = '0' and address(11 downto 10) = "11" then
- if address(9 downto 0) = "0000000000" then
- data_out(0) <= tumbl_reset;
- data_out(1) <= tumbl_int;
- data_out(2) <= tumbl_halt;
- data_out(3) <= tumbl_trace;
- data_out(4) <= tumbl_halted;
- data_out(5) <= tumbl_bad_op;
- data_out(31 downto 6) <= (others => '0');
- elsif address(9 downto 0) = "0000000010" then
- data_out <= tumbl_pc;
- elsif address(9 downto 0) = "0000000011" then
- data_out(4 downto 0) <= tumbl_halt_code;
- data_out(31 downto 5) <= (others => '0');
+ if imem_en_100m_s = '1' then
+ data_100m_o <= imem_data_o_100m_s;
+ elsif dmem_en_100m_s = '1' then
+ data_100m_o <= dmem_data_o_100m_s;
+ elsif ce_100m_i = '1' and rd_100m_i = '1' and address_100m_i(11 downto 10) = "11" then
+ if address_100m_i(9 downto 0) = "0000000000" then
+ data_100m_o(0) <= tumbl_reset_100m_s;
+ data_100m_o(1) <= tumbl_int_100m_s;
+ data_100m_o(2) <= tumbl_halt_100m_s;
+ data_100m_o(3) <= tumbl_trace_100m_s;
+ data_100m_o(4) <= tumbl_halted_100m_s;
+ data_100m_o(31 downto 5) <= (others => '0');
+ elsif address_100m_i(9 downto 0) = "0000000010" then
+ data_100m_o <= tumbl_pc_100m_s;
+ elsif address_100m_i(9 downto 0) = "0000000011" then
+ data_100m_o(4 downto 0) <= tumbl_halt_code_100m_s;
+ data_100m_o(31 downto 5) <= (others => '0');
else
- data_out <= (others => 'X');
+ data_100m_o <= (others => 'X');
end if;
else
- data_out <= (others => 'X');
+ data_100m_o <= (others => 'X');
end if;
end process;
-- Transaction acknowledge and writing to registers
-- The clock are synchronous!
- update: process(clk_100m)
+ update: process(clk_100m_i)
begin
-- Update on the 100 MHz clock
- if clk_100m = '1' and clk_100m'event then
- ta <= '1';
+ if clk_100m_i = '1' and clk_100m_i'event then
+ ta_100m_o <= '0';
- if imem_en = '1' or dmem_en = '1' then
- ta <= '0';
+ -- Copy the 50M driven signals to 100M domain
+ tumbl_pc_100m_s <= tumbl_pc_50m_s;
+ tumbl_halted_100m_s <= tumbl_halted_50m_s;
+ tumbl_halt_code_100m_s <= tumbl_halt_code_50m_s;
+
+ if imem_en_100m_s = '1' or dmem_en_100m_s = '1' then
+ ta_100m_o <= '1';
end if;
- if reset = '1' then
- tumbl_reset <= '1';
- tumbl_int <= '0';
- tumbl_halt <= '0';
- tumbl_trace <= '0';
- tumbl_trace_kick_req <= '0';
+ if reset_100m_i = '1' then
+ tumbl_reset_100m_s <= '1';
+ tumbl_int_100m_s <= '0';
+ tumbl_halt_100m_s <= '0';
+ tumbl_trace_100m_s <= '0';
+ tumbl_trace_kick_req_100m_s <= '0';
else
-
- if tumbl_trace_kick_ack = '1' then
- tumbl_trace_kick_req <= '0';
+ if tumbl_trace_kick_ack_50m_s = '1' then
+ tumbl_trace_kick_req_100m_s <= '0';
end if;
- if ce = '0' and address(11 downto 10) = "11" then
- if bls(0) = '0' then
- if address(9 downto 0) = "0000000000" then
- tumbl_reset <= data_in(0);
- tumbl_int <= data_in(1);
- tumbl_halt <= data_in(2);
- tumbl_trace <= data_in(3);
- elsif address(9 downto 0) = "0000000001" then
- if data_in(0) = '1' and tumbl_trace_kick = '0' then
- tumbl_trace_kick_req <= '1';
+ if ce_100m_i = '1' and address_100m_i(11 downto 10) = "11" then
+ if bls_100m_i(0) = '1' then
+ if address_100m_i(9 downto 0) = "0000000000" then
+ tumbl_reset_100m_s <= data_100m_i(0);
+ tumbl_int_100m_s <= data_100m_i(1);
+ tumbl_halt_100m_s <= data_100m_i(2);
+ tumbl_trace_100m_s <= data_100m_i(3);
+ elsif address_100m_i(9 downto 0) = "0000000001" then
+ if data_100m_i(0) = '1' then
+ tumbl_trace_kick_req_100m_s <= '1';
end if;
end if;
end if;
- if rd = '0' then
- ta <= '0';
+ if rd_100m_i = '1' then
+ ta_100m_o <= '1';
end if;
end if;
end if;
end process;
-- Update tracing
- tumbl: process(clk_50m)
+ tumbl: process(clk_50m_i)
begin
-- Update on the 50 MHz clock
- if clk_50m = '1' and clk_50m'event then
-
- if reset = '1' then
- tumbl_trace_kick <= '0';
- tumbl_trace_kick_ack <= '0';
+ if clk_50m_i = '1' and clk_50m_i'event then
+
+ -- Copy the 100M driven signals to their 50M domain
+ -- and then route them further
+ tumbl_reset_50m_s <= tumbl_reset_100m_s;
+ tumbl_int_50m_s <= tumbl_int_100m_s;
+ tumbl_halt_50m_s <= tumbl_halt_100m_s;
+ tumbl_trace_50m_s <= tumbl_trace_100m_s;
+
+ if reset_100m_i = '1' then
+ tumbl_trace_kick_50m_s <= '0';
+ tumbl_trace_kick_ack_50m_s <= '0';
else
- if tumbl_trace_kick = '0' and tumbl_trace_kick_req = '1' then
- tumbl_trace_kick <= '1';
- tumbl_trace_kick_ack <= '1';
+ if tumbl_trace_kick_50m_s = '0' and tumbl_trace_kick_req_100m_s = '1' then
+ tumbl_trace_kick_50m_s <= '1';
+ tumbl_trace_kick_ack_50m_s <= '1';
else
- tumbl_trace_kick <= '0';
+ tumbl_trace_kick_50m_s <= '0';
end if;
end if;
- if tumbl_trace_kick_req <= '0' then
- tumbl_trace_kick_ack <= '0';
+ if tumbl_trace_kick_req_100m_s = '0' then
+ tumbl_trace_kick_ack_50m_s <= '0';
end if;
end if;
end process;
end Behavioral;
-
entity calibration_read_register is
generic
(
- id : std_logic_vector(31 downto 0) := (others => '0')
+ id_g : std_logic_vector(31 downto 0) := (others => '0')
);
port
(
-- Data bus (read only)
- data_out : out std_logic_vector(31 downto 0);
-
+ data_o : out std_logic_vector(31 downto 0);
-- Bus signals
- rd : in std_logic;
- ta : out std_logic
+ rd_i : in std_logic;
+ ta_o : out std_logic
);
end calibration_read_register;
architecture Behavioral of calibration_read_register is
begin
- memory_bus: process(rd)
+memory_bus:
+ process(rd_i)
begin
-
- ta <= rd;
- data_out <= id;
-
+ ta_o <= rd_i;
+ data_o <= id_g;
end process;
end Behavioral;
port
(
-- Clock
- clk : in std_logic;
-
+ clk_i : in std_logic;
-- Reset
- reset : in std_logic;
-
+ reset_i : in std_logic;
-- Chip enable
- ce : in std_logic;
-
+ ce_i : in std_logic;
-- Data bus
- data_in : in std_logic_vector(31 downto 0);
- data_out : out std_logic_vector(31 downto 0);
-
+ data_i : in std_logic_vector(31 downto 0);
+ data_o : out std_logic_vector(31 downto 0);
-- Bus signals
- rd : in std_logic;
- bls : in std_logic_vector(3 downto 0);
- ta : out std_logic
+ rd_i : in std_logic;
+ bls_i : in std_logic_vector(3 downto 0);
+ ta_o : out std_logic
);
end calibration_write_register;
architecture Behavioral of calibration_write_register is
- signal value : std_logic_vector(31 downto 0);
+ signal value_s : std_logic_vector(31 downto 0);
begin
-- Read is immideate
- memory_bus_read: process(rd, value)
+ memory_bus_read: process(rd_i, value_s)
begin
-
- ta <= rd;
- data_out <= value;
-
+ ta_o <= rd_i;
+ data_o <= value_s;
end process;
-- Write waits for clock
- memory_bus_write: process(clk)
+ memory_bus_write: process(clk_i)
begin
- if clk = '1' and clk'event then
+ if clk_i = '1' and clk_i'event then
- if reset = '1' then
- value <= (others => '0');
- end if;
+ if reset_i = '1' then
+ value_s <= (others => '0');
+ else
- if ce = '0' then
+ if ce_i = '1' and bls_i /= "0000" then
- if reset = '0' and bls /= "1111" then
-
- if bls(0) = '0' then
- value(7 downto 0) <= data_in(7 downto 0);
+ if bls_i(0) = '1' then
+ value_s(7 downto 0) <= data_i(7 downto 0);
end if;
-
- if bls(1) = '0' then
- value(15 downto 8) <= data_in(15 downto 8);
+ if bls_i(1) = '1' then
+ value_s(15 downto 8) <= data_i(15 downto 8);
end if;
-
- if bls(2) = '0' then
- value(23 downto 16) <= data_in(23 downto 16);
+ if bls_i(2) = '1' then
+ value_s(23 downto 16) <= data_i(23 downto 16);
end if;
-
- if bls(3) = '0' then
- value(31 downto 24) <= data_in(31 downto 24);
+ if bls_i(3) = '1' then
+ value_s(31 downto 24) <= data_i(31 downto 24);
end if;
end if;
-
end if;
-
end if;
end process;
entity dff is
port
(
- clk : in std_logic;
- reset : in std_logic;
- d : in std_logic;
- q : out std_logic
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ d_i : in std_logic;
+ q_o : out std_logic
);
-end dff;
+end dff2;
architecture behavioral of dff is
- signal data: std_logic;
begin
- q <= data;
- seq: process(clk)
- begin
- if clk = '1' and clk'event then
- if reset = '1' then
- data <= '0';
+seq:
+ process(clk_i)
+ begin
+ if clk_i = '1' and clk_i'event then
+ if reset_i = '1' then
+ q_o <= '0';
else
- data <= d;
+ q_o <= d_i;
end if;
end if;
end process;
entity dff2 is
port
(
- clk : in std_logic;
- reset : in std_logic;
- d : in std_logic;
- q : out std_logic
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ d_i : in std_logic;
+ q_o : out std_logic
);
end dff2;
architecture behavioral of dff2 is
- signal last_d : std_logic;
- signal data: std_logic;
+ signal last_d_s : std_logic;
+ signal data_s : std_logic;
begin
- q <= data;
+ q_o <= data_s;
- seq: process(clk)
- begin
- if clk = '1' and clk'event then
- if reset = '1' then
- last_d <= '0';
- data <= '0';
+seq:
+ process(clk_i)
+ begin
+ if clk_i = '1' and clk_i'event then
+ if reset_i = '1' then
+ last_d_s <= '0';
+ data_s <= '0';
else
- if d = last_d then
- data <= d;
+ if d_i = last_d_s then
+ data_s <= d_i;
end if;
end if;
- last_d <= d;
+ last_d_s <= d_i;
end if;
end process;
entity irc_reader is
port
(
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- index0 : in std_logic;
- mark0 : in std_logic;
-
- qcount : out std_logic_vector (31 downto 0);
- qcount_index : out std_logic_vector (31 downto 0);
- ab_event : out std_logic;
- ab_error : out std_logic;
- out_mark : out std_logic
+ -- Inputs
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ a0_i, b0_i : in std_logic;
+ index0_i : in std_logic;
+ mark0_i : in std_logic;
+ -- Outputs
+ qcount_o : out std_logic_vector (31 downto 0);
+ qcount_index_o : out std_logic_vector (31 downto 0);
+ ab_error_o : out std_logic;
+ mark_o : out std_logic
);
end irc_reader;
dff_mark: dff2
port map
(
- clk => clk,
- reset => '0',
- d => mark0,
- q => out_mark
+ clk_i => clk_i,
+ reset_i => '0',
+ d_i => mark0_i,
+ q_o => mark_o
);
qctr: qcounter
port map
(
- clk => clk,
- reset => reset,
- a0 => a0,
- b0 => b0,
- index0 => index0,
- qcount => qcount,
- qcount_index => qcount_index,
- ab_event => ab_event,
- ab_error => ab_error,
- a_rise => open,
- a_fall => open,
- b_rise => open,
- b_fall => open
+ clk_i => clk_i,
+ reset_i => reset_i,
+ a0_i => a0_i,
+ b0_i => b0_i,
+ index0_i => index0_i,
+ qcount_o => qcount_o,
+ qcount_index_o => qcount_index_o,
+ ab_error_o => ab_error_o,
+ ab_event_o => open,
+ a_rise_o => open,
+ a_fall_o => open,
+ b_rise_o => open,
+ b_fall_o => open
);
end rtl;
entity irc_register is
port
(
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- index0 : in std_logic;
- mark0 : in std_logic;
-
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ a0_i, b0_i : in std_logic;
+ index0_i : in std_logic;
+ mark0_i : in std_logic;
-- Data bus for Master CPU
- data_in : in std_logic; -- 1 bit input
- data_out : out std_logic_vector(31 downto 0);
-
+ data_i : in std_logic; -- 1 bit input
+ data_o : out std_logic_vector(31 downto 0);
-- Chip Enable signal (two registers; one for IRC counter (readonly) other for status (R/W))
- ce : in std_logic_vector(1 downto 0);
-
+ ce_i : in std_logic_vector(1 downto 0);
-- Reading / writing signals (needs only one byte for writing)
- rd : in std_logic;
- ta : out std_logic;
- wr : in std_logic
+ rd_i : in std_logic;
+ ta_o : out std_logic;
+ wr_i : in std_logic
);
end irc_register;
architecture Behavioral of irc_register is
- signal qcount_error : std_logic;
- signal qcount : std_logic_vector (31 downto 0);
- signal qcount_index : std_logic_vector (31 downto 0);
- signal ab_event : std_logic;
- signal ab_error : std_logic;
- signal out_mark : std_logic;
-
- component irc_reader
- port
- (
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- index0 : in std_logic;
- mark0 : in std_logic;
-
- qcount : out std_logic_vector (31 downto 0);
- qcount_index : out std_logic_vector (31 downto 0);
- ab_event : out std_logic;
- ab_error : out std_logic;
- out_mark : out std_logic
- );
- end component;
+
+ signal qcount_error_s : std_logic;
+ signal qcount_s : std_logic_vector (31 downto 0);
+ signal qcount_index_s : std_logic_vector (31 downto 0);
+ signal ab_event_s : std_logic;
+ signal ab_error_s : std_logic;
+ signal mark_s : std_logic;
begin
reader: irc_reader
port map
(
- clk => clk,
- reset => reset,
- a0 => a0,
- b0 => b0,
- index0 => index0,
- mark0 => mark0,
- qcount => qcount,
- qcount_index => qcount_index,
- ab_event => ab_event,
- ab_error => ab_error,
- out_mark => out_mark
+ clk_i => clk_i,
+ reset_i => reset_i,
+ a0_i => a0_i,
+ b0_i => b0_i,
+ index0_i => index0_i,
+ mark0_i => mark0_i,
+ qcount_o => qcount_s,
+ qcount_index_o => qcount_index_s,
+ ab_error_o => ab_error_s,
+ mark_o => mark_s
);
- update: process(clk)
+update:
+ process(clk_i)
begin
- if clk = '1' and clk'event then
+ if clk_i = '1' and clk_i'event then
-- Latches using it's own value - requires synchronous handling
- if (reset = '1') or (ce = "10" and wr = '0' and data_in = '0') then
- qcount_error <= '0';
+ if (reset_i = '1') or (ce_i = "10" and wr_i = '1' and data_i = '1') then
+ qcount_error_s <= '0';
else
- qcount_error <= qcount_error or ab_error;
+ qcount_error_s <= qcount_error_s or ab_error_s;
end if;
end if;
end process;
-
- memory_bus: process(ce, rd, qcount, qcount_index, qcount_error, ab_event, ab_error, out_mark)
+memory_bus:
+ process(ce_i, rd_i, qcount_s, qcount_index_s, qcount_error_s, ab_error_s, mark_s)
begin
-- Reset signals
- ta <= rd;
- data_out <= (others => 'X');
+ ta_o <= rd_i;
+ data_o <= (others => 'X');
-- Check chip enable
- case ce is
+ case ce_i is
when "00" =>
- data_out <= qcount;
+ data_o <= qcount_s;
when "01" =>
- data_out <= qcount_index;
+ data_o <= qcount_index_s;
when "10" =>
- data_out(0) <= ab_event;
- data_out(1) <= ab_error;
- data_out(2) <= qcount_error;
- data_out(3) <= out_mark;
- data_out(31 downto 4) <= (others => '0');
+ data_o(0) <= qcount_error_s;
+ data_o(1) <= mark_s;
+ data_o(31 downto 2) <= (others => '0');
when others => NULL;
end process;
end Behavioral;
-
bgti r18, .Lloopdata
.Lenddata:
/* Init default values */
- brli r15, init_defvals
+ brli r15, init_defvals
/* Run program */
- brli r15, main
+ brli r15, main
/* End of program */
halt 0
bsel_i : in std_logic_vector(3 downto 0);
dat_i : in std_logic_vector(31 downto 0);
dat_o : out std_logic_vector(31 downto 0);
-
-- Memory wiring for Master CPU
clk_m : in std_logic;
en_m : in std_logic;
addr_m : in std_logic_vector(9 downto 0);
din_m : in std_logic_vector(31 downto 0);
dout_m : out std_logic_vector(31 downto 0)
-
);
end lx_rocon_dmem;
clk_i : in std_logic;
rst_i : in std_logic;
clken_i : in std_logic;
-
+ --
ID2GPRF_i : in ID2GPRF_Type;
MEM_WRB_i : in WRB_Type;
GPRF2EX_o : out GPRF2EX_Type
port
(
-- Memory wiring for Tumbl
- clk_i : in std_logic;
- cs_i : in std_logic;
- adr_i : in std_logic_vector(10 downto 2);
- dat_o : out std_logic_vector(31 downto 0);
-
+ clk_i : in std_logic;
+ cs_i : in std_logic;
+ adr_i : in std_logic_vector(10 downto 2);
+ dat_o : out std_logic_vector(31 downto 0);
-- Memory wiring for Master CPU
clk_m : in std_logic;
en_m : in std_logic;
addr_m : in std_logic_vector(8 downto 0);
din_m : in std_logic_vector(31 downto 0);
dout_m : out std_logic_vector(31 downto 0)
-
);
end lx_rocon_imem;
entity lx_rocon_tumbl is
generic
(
- IMEM_ABITS_g : positive := 11;
- DMEM_ABITS_g : positive := 12;
+ IMEM_ABITS_g : positive := 11;
+ DMEM_ABITS_g : positive := 12;
--
- USE_HW_MUL_g : boolean := true;
- USE_BARREL_g : boolean := true;
+ USE_HW_MUL_g : boolean := true;
+ USE_BARREL_g : boolean := true;
COMPATIBILITY_MODE_g : boolean := false
);
port
int_i : in std_logic;
trace_i : in std_logic;
trace_kick_i : in std_logic;
-
-- Program counter
pc_o : out std_logic_vector(31 downto 0);
-
-- Internal halt (remove with trace kick)
halted_o : out std_logic;
halt_code_o : out std_logic_vector(4 downto 0);
-
-- Internal memory (instruction)
- imem_clk : in std_logic;
- imem_en : in std_logic;
- imem_we : in std_logic_vector(3 downto 0);
- imem_addr : in std_logic_vector(8 downto 0);
- imem_din : in std_logic_vector(31 downto 0);
- imem_dout : out std_logic_vector(31 downto 0);
-
+ imem_clk_i : in std_logic;
+ imem_en_i : in std_logic;
+ imem_we_i : in std_logic_vector(3 downto 0);
+ imem_addr_i : in std_logic_vector(8 downto 0);
+ imem_data_i : in std_logic_vector(31 downto 0);
+ imem_data_o : out std_logic_vector(31 downto 0);
-- Internal memory (data)
- dmem_clk : in std_logic;
- dmem_en : in std_logic;
- dmem_we : in std_logic_vector(3 downto 0);
- dmem_addr : in std_logic_vector(9 downto 0);
- dmem_din : in std_logic_vector(31 downto 0);
- dmem_dout : out std_logic_vector(31 downto 0);
-
+ dmem_clk_i : in std_logic;
+ dmem_en_i : in std_logic;
+ dmem_we_i : in std_logic_vector(3 downto 0);
+ dmem_addr_i : in std_logic_vector(9 downto 0);
+ dmem_data_i : in std_logic_vector(31 downto 0);
+ dmem_data_o : out std_logic_vector(31 downto 0);
-- External memory bus
- XMEMB_sel_o : out std_logic;
- XMEMB_i : in DMEMB2CORE_Type;
- XMEMB_o : out CORE2DMEMB_Type;
- --
- bad_op_o : out std_logic
+ XMEMB_sel_o : out std_logic;
+ XMEMB_i : in DMEMB2CORE_Type;
+ XMEMB_o : out CORE2DMEMB_Type
);
end entity lx_rocon_tumbl;
signal IF2ID_s, IF2ID_r : IF2ID_Type;
signal ID2EX_s, ID2EX_r : ID2EX_Type;
+ signal delay_bit_r : std_logic;
signal ID2GPRF_s : ID2GPRF_Type;
signal GPRF2EX_s : GPRF2EX_Type;
signal EX2IF_s, EX2IF_r : EX2IF_Type;
signal MSR2EX_s : MSR_Type;
signal MEM_REG_s, MEM_REG_r : MEM_REG_Type;
signal dmem_sel_s, dmem_sel_r : std_logic;
- signal bad_op_s : std_logic;
signal HALT_s : HALT_Type;
signal ext_halt_s : std_logic;
pc_o <= ID2EX_r.program_counter; -- Program counter for EXEQ
halted_o <= HALT_s.halt;
halt_code_o <= HALT_s.halt_code;
- bad_op_o <= bad_op_s;
ext_halt_s <= halt_i;
imem_really_clken_s <= imem_clken_s and core_clken_s;
I_IMEM: lx_rocon_imem
port map
(
- clk_i => clk_i,
- cs_i => imem_really_clken_s,
- adr_i => imem_addr_s((IMEM_ABITS_g-1) downto 2),
- dat_o => imem_data_s,
+ clk_i => clk_i,
+ cs_i => imem_really_clken_s,
+ adr_i => imem_addr_s((IMEM_ABITS_g-1) downto 2),
+ dat_o => imem_data_s,
- clk_m => imem_clk,
- en_m => imem_en,
- we_m => imem_we,
- addr_m => imem_addr,
- din_m => imem_din,
- dout_m => imem_dout
+ clk_m => imem_clk_i,
+ en_m => imem_en_i,
+ we_m => imem_we_i,
+ addr_m => imem_addr_i,
+ din_m => imem_data_i,
+ dout_m => imem_data_o
);
I_DMEM: lx_rocon_dmem
dat_i => c2dmemb_s.data,
dat_o => dmem_data_s,
- clk_m => dmem_clk,
- en_m => dmem_en,
- we_m => dmem_we,
- addr_m => dmem_addr,
- din_m => dmem_din,
- dout_m => dmem_dout
+ clk_m => dmem_clk_i,
+ en_m => dmem_en_i,
+ we_m => dmem_we_i,
+ addr_m => dmem_addr_i,
+ din_m => dmem_data_i,
+ dout_m => dmem_data_o
);
I_FETCH: fetch
ID2EX_o => ID2EX_s,
--
INT_CTRL_i => INT_CTRL_s,
- ID2CTRL_o => ID2CTRL_s,
- --
- noLiteOpc_o => bad_op_s
+ ID2CTRL_o => ID2CTRL_s
);
I_GPRF: lx_rocon_gprf_abd
generic map(USE_HW_MUL_g, USE_BARREL_g, COMPATIBILITY_MODE_g)
port map
(
+ IF2ID_i => IF2ID_r,
+ --
ID2EX_i => ID2EX_r,
+ delayBit_i => delay_bit_r,
GPRF2EX_i => GPRF2EX_s,
EX2IF_o => EX2IF_s,
EX2CTRL_o => EX2CTRL_s,
clk_i => clk_i,
rst_i => rst_i,
halt_i => ext_halt_s,
- bad_op_i => bad_op_s,
int_i => int_i,
trace_i => trace_i,
trace_kick_i => trace_kick_i,
-- decode to exeq pipeline registers
ID2EX_REG_i => ID2EX_s,
ID2EX_REG_o => ID2EX_r,
+ delay_bit_o => delay_bit_r,
-- GPRF control
gprf_clken_o => gprf_clken_s,
-- exeq to fetch feedback registers
+++ /dev/null
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-USE work.mbl_Pkg.ALL;
-USE work.lx_rocon_pkg.ALL;
-
--- Tumbl core testbench
-
-ENTITY lx_rocon_tumbl_tb IS
-END lx_rocon_tumbl_tb;
-
-ARCHITECTURE behavior OF lx_rocon_tumbl_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT lx_rocon_tumbl
- PORT(
- clk_i : IN std_logic;
- rst_i : IN std_logic;
- halt_i : IN std_logic;
- int_i : IN std_logic;
- trace_i : IN std_logic;
- trace_kick_i : IN std_logic;
- pc_o : OUT std_logic_vector(31 downto 0);
- imem_clk : IN std_logic;
- imem_en : IN std_logic;
- imem_we : IN std_logic_vector(3 downto 0);
- imem_addr : IN std_logic_vector(8 downto 0);
- imem_din : IN std_logic_vector(31 downto 0);
- imem_dout : OUT std_logic_vector(31 downto 0);
- dmem_clk : IN std_logic;
- dmem_en : IN std_logic;
- dmem_we : IN std_logic_vector(3 downto 0);
- dmem_addr : IN std_logic_vector(9 downto 0);
- dmem_din : IN std_logic_vector(31 downto 0);
- dmem_dout : OUT std_logic_vector(31 downto 0);
- XMEMB_sel_o : OUT std_logic;
- XMEMB_i : IN DMEMB2CORE_Type;
- XMEMB_o : OUT CORE2DMEMB_Type;
- bad_op_o : OUT std_logic;
- done_o : OUT std_logic
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk_i : std_logic := '0';
- signal rst_i : std_logic := '0';
- signal halt_i : std_logic := '0';
- signal int_i : std_logic := '0';
- signal trace_i : std_logic := '0';
- signal trace_kick_i : std_logic := '0';
- signal imem_clk : std_logic := '0';
- signal imem_en : std_logic := '0';
- signal imem_we : std_logic_vector(3 downto 0) := (others => '0');
- signal imem_addr : std_logic_vector(8 downto 0) := (others => '0');
- signal imem_din : std_logic_vector(31 downto 0) := (others => '0');
- signal dmem_clk : std_logic := '0';
- signal dmem_en : std_logic := '0';
- signal dmem_we : std_logic_vector(3 downto 0) := (others => '0');
- signal dmem_addr : std_logic_vector(9 downto 0) := (others => '0');
- signal dmem_din : std_logic_vector(31 downto 0) := (others => '0');
- signal XMEMB_i : DMEMB2CORE_Type := (clken => '0', data => (others => '0'), int => '0');
-
- --Outputs
- signal pc_o : std_logic_vector(31 downto 0);
- signal imem_dout : std_logic_vector(31 downto 0);
- signal dmem_dout : std_logic_vector(31 downto 0);
- signal XMEMB_sel_o : std_logic;
- signal XMEMB_o : CORE2DMEMB_Type;
- signal bad_op_o : std_logic;
- signal done_o : std_logic;
-
- -- Clock period definitions
- constant clk_i_period : time := 20 ns; -- 50 MHz
- constant imem_clk_period : time := 13.8 ns; -- 72 MHz
- constant dmem_clk_period : time := 13.8 ns; -- 72 MHz
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: lx_rocon_tumbl PORT MAP (
- clk_i => clk_i,
- rst_i => rst_i,
- halt_i => halt_i,
- int_i => int_i,
- trace_i => trace_i,
- trace_kick_i => trace_kick_i,
- pc_o => pc_o,
- imem_clk => imem_clk,
- imem_en => imem_en,
- imem_we => imem_we,
- imem_addr => imem_addr,
- imem_din => imem_din,
- imem_dout => imem_dout,
- dmem_clk => dmem_clk,
- dmem_en => dmem_en,
- dmem_we => dmem_we,
- dmem_addr => dmem_addr,
- dmem_din => dmem_din,
- dmem_dout => dmem_dout,
- XMEMB_sel_o => XMEMB_sel_o,
- XMEMB_i => XMEMB_i,
- XMEMB_o => XMEMB_o,
- bad_op_o => bad_op_o,
- done_o => done_o
- );
-
- -- Clock process definitions
- clk_i_process :process
- begin
- clk_i <= '0';
- wait for clk_i_period/2;
- clk_i <= '1';
- wait for clk_i_period/2;
- end process;
-
- imem_clk_process :process
- begin
- imem_clk <= '0';
- wait for imem_clk_period/2;
- imem_clk <= '1';
- wait for imem_clk_period/2;
- end process;
-
- dmem_clk_process :process
- begin
- dmem_clk <= '0';
- wait for dmem_clk_period/2;
- dmem_clk <= '1';
- wait for dmem_clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- External ModelSim script
-
- wait;
- end process;
-
-END;
component irc_register
port
(
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- index0 : in std_logic;
- mark0 : in std_logic;
- data_in : in std_logic;
- data_out : out std_logic_vector(31 downto 0);
- ce : in std_logic_vector(1 downto 0);
- rd : in std_logic;
- ta : out std_logic;
- wr : in std_logic
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ a0_i, b0_i : in std_logic;
+ index0_i : in std_logic;
+ mark0_i : in std_logic;
+ -- Data bus for Master CPU
+ data_i : in std_logic; -- 1 bit input
+ data_o : out std_logic_vector(31 downto 0);
+ -- Chip Enable signal (two registers; one for IRC counter (readonly) other for status (R/W))
+ ce_i : in std_logic_vector(1 downto 0);
+ -- Reading / writing signals (needs only one byte for writing)
+ rd_i : in std_logic;
+ ta_o : out std_logic;
+ wr_i : in std_logic
);
end component;
- -- BCD counter
- component bcd
- generic
- (
- width : integer
- );
+ -- IRC reader
+ component irc_reader
port
(
- reset : in std_logic;
- en : in std_logic;
- clk : in std_logic;
- value : out std_logic_vector((width-1) downto 0)
- );
+ -- Inputs
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ a0_i, b0_i : in std_logic;
+ index0_i : in std_logic;
+ mark0_i : in std_logic;
+ -- Outputs
+ qcount_o : out std_logic_vector (31 downto 0);
+ qcount_index_o : out std_logic_vector (31 downto 0);
+ ab_error_o : out std_logic;
+ mark_o : out std_logic
+ );
end component;
-- Quadcount
component qcounter
port
(
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- index0 : in std_logic;
-
- a_rise : out std_logic;
- a_fall : out std_logic;
- b_rise : out std_logic;
- b_fall : out std_logic;
-
- qcount : out std_logic_vector (31 downto 0);
- qcount_index : out std_logic_vector (31 downto 0);
- ab_event : out std_logic;
- ab_error : out std_logic
- );
+ -- Inputs
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ a0_i, b0_i : in std_logic;
+ index0_i : in std_logic;
+ -- Outputs
+ qcount_o : out std_logic_vector (31 downto 0);
+ qcount_index_o : out std_logic_vector (31 downto 0);
+ a_rise_o, a_fall_o : out std_logic;
+ b_rise_o, b_fall_o : out std_logic;
+ ab_event_o : out std_logic;
+ ab_error_o : out std_logic
+ );
end component;
-- D sampler
component dff
port
(
- clk : in std_logic;
- reset : in std_logic;
- d : in std_logic;
- q : out std_logic
- );
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ d_i : in std_logic;
+ q_o : out std_logic
+ );
end component;
-- D sampler (filtered)
component dff2
port
(
- clk : in std_logic;
- reset : in std_logic;
- d : in std_logic;
- q : out std_logic
- );
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ d_i : in std_logic;
+ q_o : out std_logic
+ );
end component;
--------------------------------------------------------------------------------
component lx_rocon_tumbl
generic
(
- IMEM_ABITS_g : positive := 12;
- DMEM_ABITS_g : positive := 12;
+ IMEM_ABITS_g : positive := 11;
+ DMEM_ABITS_g : positive := 12;
--
- USE_HW_MUL_g : boolean := true;
- USE_BARREL_g : boolean := true;
- COMPATIBILITY_MODE_g : boolean := false
+ USE_HW_MUL_g : boolean := true;
+ USE_BARREL_g : boolean := true;
+ COMPATIBILITY_MODE_g : boolean := false
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
- halt_i : in std_logic;
+ halt_i : in std_logic;
int_i : in std_logic;
trace_i : in std_logic;
trace_kick_i : in std_logic;
- pc_o : out std_logic_vector(31 downto 0);
+ -- Program counter
+ pc_o : out std_logic_vector(31 downto 0);
+ -- Internal halt (remove with trace kick)
halted_o : out std_logic;
halt_code_o : out std_logic_vector(4 downto 0);
- imem_clk : in std_logic;
- imem_en : in std_logic;
- imem_we : in std_logic_vector(3 downto 0);
- imem_addr : in std_logic_vector(8 downto 0);
- imem_din : in std_logic_vector(31 downto 0);
- imem_dout : out std_logic_vector(31 downto 0);
- dmem_clk : in std_logic;
- dmem_en : in std_logic;
- dmem_we : in std_logic_vector(3 downto 0);
- dmem_addr : in std_logic_vector(9 downto 0);
- dmem_din : in std_logic_vector(31 downto 0);
- dmem_dout : out std_logic_vector(31 downto 0);
- XMEMB_sel_o : out std_logic;
- XMEMB_i : in DMEMB2CORE_Type;
- XMEMB_o : out CORE2DMEMB_Type;
- bad_op_o : out std_logic
+ -- Internal memory (instruction)
+ imem_clk_i : in std_logic;
+ imem_en_i : in std_logic;
+ imem_we_i : in std_logic_vector(3 downto 0);
+ imem_addr_i : in std_logic_vector(8 downto 0);
+ imem_data_i : in std_logic_vector(31 downto 0);
+ imem_data_o : out std_logic_vector(31 downto 0);
+ -- Internal memory (data)
+ dmem_clk_i : in std_logic;
+ dmem_en_i : in std_logic;
+ dmem_we_i : in std_logic_vector(3 downto 0);
+ dmem_addr_i : in std_logic_vector(9 downto 0);
+ dmem_data_i : in std_logic_vector(31 downto 0);
+ dmem_data_o : out std_logic_vector(31 downto 0);
+ -- External memory bus
+ XMEMB_sel_o : out std_logic;
+ XMEMB_i : in DMEMB2CORE_Type;
+ XMEMB_o : out CORE2DMEMB_Type
);
end component;
component lx_rocon_imem
port
(
- clk_i : in std_logic;
- cs_i : in std_logic;
- adr_i : in std_logic_vector(10 downto 2);
- dat_o : out std_logic_vector(31 downto 0);
+ -- Memory wiring for Tumbl
+ clk_i : in std_logic;
+ cs_i : in std_logic;
+ adr_i : in std_logic_vector(10 downto 2);
+ dat_o : out std_logic_vector(31 downto 0);
+ -- Memory wiring for Master CPU
clk_m : in std_logic;
en_m : in std_logic;
we_m : in std_logic_vector(3 downto 0);
addr_m : in std_logic_vector(8 downto 0);
din_m : in std_logic_vector(31 downto 0);
dout_m : out std_logic_vector(31 downto 0)
-
);
end component;
component lx_rocon_dmem
port
(
+ -- Memory wiring for Tumbl
clk_i : in std_logic;
ce_i : in std_logic;
adr_i : in std_logic_vector(11 downto 2);
bsel_i : in std_logic_vector(3 downto 0);
dat_i : in std_logic_vector(31 downto 0);
dat_o : out std_logic_vector(31 downto 0);
+ -- Memory wiring for Master CPU
clk_m : in std_logic;
en_m : in std_logic;
we_m : in std_logic_vector(3 downto 0);
clk_i : in std_logic;
rst_i : in std_logic;
clken_i : in std_logic;
+ --
ID2GPRF_i : in ID2GPRF_Type;
MEM_WRB_i : in WRB_Type;
GPRF2EX_o : out GPRF2EX_Type
component calibration_read_register
generic
(
- id : std_logic_vector(31 downto 0)
+ id_g : std_logic_vector(31 downto 0) := (others => '0')
);
port
(
- data_out : out std_logic_vector(31 downto 0);
- rd : in std_logic;
- ta : out std_logic
+ -- Data bus (read only)
+ data_o : out std_logic_vector(31 downto 0);
+ -- Bus signals
+ rd_i : in std_logic;
+ ta_o : out std_logic
);
end component;
component calibration_write_register
port
(
- clk : in std_logic;
- reset : in std_logic;
- ce : in std_logic;
- data_in : in std_logic_vector(31 downto 0);
- data_out : out std_logic_vector(31 downto 0);
- rd : in std_logic;
- bls : in std_logic_vector(3 downto 0);
- ta : out std_logic
+ -- Clock
+ clk_i : in std_logic;
+ -- Reset
+ reset_i : in std_logic;
+ -- Chip enable
+ ce_i : in std_logic;
+ -- Data bus
+ data_i : in std_logic_vector(31 downto 0);
+ data_o : out std_logic_vector(31 downto 0);
+ -- Bus signals
+ rd_i : in std_logic;
+ bls_i : in std_logic_vector(3 downto 0);
+ ta_o : out std_logic
);
end component;
component bus_calibration
port
(
- clk : in std_logic;
- reset : in std_logic;
- ce : in std_logic;
- address : in std_logic_vector(1 downto 0);
- data_in : in std_logic_vector(31 downto 0);
- data_out : out std_logic_vector(31 downto 0);
- rd : in std_logic;
- bls : in std_logic_vector(3 downto 0);
- ta : out std_logic
+ -- Clock
+ clk_i : in std_logic;
+ -- Reset
+ reset_i : in std_logic;
+ -- Chip enable
+ ce_i : in std_logic;
+ -- Address
+ address_i : in std_logic_vector(1 downto 0);
+ -- Data bus
+ data_i : in std_logic_vector(31 downto 0);
+ data_o : out std_logic_vector(31 downto 0);
+ -- Bus signals
+ rd_i : in std_logic;
+ bls_i : in std_logic_vector(3 downto 0);
+ ta_o : out std_logic
);
end component;
component bus_irc
port
(
- clk : in std_logic;
- reset : in std_logic;
-
- address : in std_logic_vector(3 downto 0);
- ce : in std_logic;
-
- data_in : in std_logic;
- data_out : out std_logic_vector(31 downto 0);
-
- rd : in std_logic;
- wr : in std_logic;
- ta : out std_logic;
-
- irc1_a : in std_logic;
- irc1_b : in std_logic;
- irc1_index : in std_logic;
- irc1_mark : in std_logic;
-
- irc2_a : in std_logic;
- irc2_b : in std_logic;
- irc2_index : in std_logic;
- irc2_mark : in std_logic;
-
- irc3_a : in std_logic;
- irc3_b : in std_logic;
- irc3_index : in std_logic;
- irc3_mark : in std_logic;
-
- irc4_a : in std_logic;
- irc4_b : in std_logic;
- irc4_index : in std_logic;
- irc4_mark : in std_logic
- );
- end component;
-
- -- BCD interconnect
- component bus_bcd
- port
- (
- reset : in std_logic;
- en : in std_logic;
- clk : in std_logic;
- data_out : out std_logic_vector(31 downto 0);
- rd : in std_logic;
- ta : out std_logic
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ -- Address (needs just last 4 bits, rest is wired to CE)
+ address_i : in std_logic_vector(3 downto 0);
+ ce_i : in std_logic;
+ -- Data bus
+ data_i : in std_logic; -- 1 bit input
+ data_o : out std_logic_vector(31 downto 0);
+ -- Bus signals
+ rd_i : in std_logic;
+ ta_o : out std_logic;
+ wr_i : in std_logic;
+ -- Signals for IRC
+ irc1_a_i : in std_logic;
+ irc1_b_i : in std_logic;
+ irc1_index_i : in std_logic;
+ irc1_mark_i : in std_logic;
+ --
+ irc2_a_i : in std_logic;
+ irc2_b_i : in std_logic;
+ irc2_index_i : in std_logic;
+ irc2_mark_i : in std_logic;
+ --
+ irc3_a_i : in std_logic;
+ irc3_b_i : in std_logic;
+ irc3_index_i : in std_logic;
+ irc3_mark_i : in std_logic;
+ --
+ irc4_a_i : in std_logic;
+ irc4_b_i : in std_logic;
+ irc4_index_i : in std_logic;
+ irc4_mark_i : in std_logic
);
end component;
component bus_tumbl
port
(
- clk_100m : in std_logic;
- clk_50m : in std_logic;
- ce : in std_logic;
- reset : in std_logic;
- rd : in std_logic;
- bls : in std_logic_vector(3 downto 0);
- address : in std_logic_vector(11 downto 0);
- data_in : in std_logic_vector(31 downto 0);
- data_out : out std_logic_vector(31 downto 0);
- ta : out std_logic;
- XMEMB_sel_o : out std_logic;
- XMEMB_i : in DMEMB2CORE_Type;
- XMEMB_o : out CORE2DMEMB_Type
+ -- Clock
+ clk_100m_i : in std_logic;
+ clk_50m_i : in std_logic;
+ -- Chip enable
+ ce_100m_i : in std_logic;
+ -- Global Reset
+ reset_100m_i : in std_logic;
+ -- Master CPU bus for the memory
+ rd_100m_i : in std_logic;
+ bls_100m_i : in std_logic_vector(3 downto 0);
+ address_100m_i : in std_logic_vector(11 downto 0);
+ data_100m_i : in std_logic_vector(31 downto 0);
+ data_100m_o : out std_logic_vector(31 downto 0);
+ ta_100m_o : out std_logic;
+ -- Tumbl extrenal memory bus
+ XMEMB_sel_50m_o : out std_logic;
+ XMEMB_50m_i : in DMEMB2CORE_Type;
+ XMEMB_50m_o : out CORE2DMEMB_Type
);
end component;
component xilinx_dualport_bram
generic
(
- byte_width : positive := 8;
+ byte_width : positive := 8;
address_width : positive := 8;
- we_width : positive := 4
+ we_width : positive := 4
);
port
(
- clka : in std_logic;
- rsta : in std_logic;
- ena : in std_logic;
- wea : in std_logic_vector((we_width-1) downto 0);
+ clka : in std_logic;
+ rsta : in std_logic;
+ ena : in std_logic;
+ wea : in std_logic_vector((we_width-1) downto 0);
addra : in std_logic_vector((address_width-1) downto 0);
- dina : in std_logic_vector(((byte_width*we_width)-1) downto 0);
+ dina : in std_logic_vector(((byte_width*we_width)-1) downto 0);
douta : out std_logic_vector(((byte_width*we_width)-1) downto 0);
- clkb : in std_logic;
- rstb : in std_logic;
- enb : in std_logic;
- web : in std_logic_vector((we_width-1) downto 0);
+ clkb : in std_logic;
+ rstb : in std_logic;
+ enb : in std_logic;
+ web : in std_logic_vector((we_width-1) downto 0);
addrb : in std_logic_vector((address_width-1) downto 0);
- dinb : in std_logic_vector(((byte_width*we_width)-1) downto 0);
+ dinb : in std_logic_vector(((byte_width*we_width)-1) downto 0);
doutb : out std_logic_vector(((byte_width*we_width)-1) downto 0)
);
end component;
package body lx_rocon_pkg is
-
end lx_rocon_pkg;
vhdl work "tumbl/mbl_Pkg.vhd"
vhdl work "lx_rocon_pkg.vhd"
+vhdl work "dff2.vhd"
vhdl work "xilinx_dualport_bram.vhd"
+vhdl work "qcounter.vhd"
vhdl work "tumbl/mem.vhd"
vhdl work "tumbl/fetch.vhd"
vhdl work "tumbl/exeq.vhd"
vhdl work "lx-rocon_tumbl/lx_rocon_imem.vhd"
vhdl work "lx-rocon_tumbl/lx_rocon_gprf_abd.vhd"
vhdl work "lx-rocon_tumbl/lx_rocon_dmem.vhd"
+vhdl work "irc_reader.vhd"
vhdl work "lx-rocon_tumbl/lx_rocon_tumbl.vhd"
+vhdl work "irc_register.vhd"
vhdl work "calibration_write_register.vhd"
vhdl work "calibration_read_register.vhd"
vhdl work "bus_tumbl.vhd"
+vhdl work "bus_irc.vhd"
vhdl work "bus_calibration.vhd"
vhdl work "lx_rocon_top.vhd"
port
(
-- External
- --clk_cpu : in std_logic;
- clk_50m : in std_logic;
+ --clk_cpu : in std_logic;
+ clk_50m : in std_logic;
- cs0_xc : in std_logic;
+ cs0_xc : in std_logic;
- rd : in std_logic;
- bls : in std_logic_vector(3 downto 0);
- address : in std_logic_vector(15 downto 0);
- data : inout std_logic_vector(31 downto 0);
+ rd : in std_logic;
+ bls : in std_logic_vector(3 downto 0);
+ address : in std_logic_vector(15 downto 0);
+ data : inout std_logic_vector(31 downto 0);
irc1_a : in std_logic;
irc1_b : in std_logic;
architecture Behavioral of lx_rocon_top is
-- Reset signal
- signal reset : std_logic;
- signal neg_init : std_logic;
-
+ signal reset_s : std_logic;
+ signal neg_init_s : std_logic;
-- 100 MHz clock
- signal clk_100m : std_logic;
- signal clk_100m_fb : std_logic;
- signal clk_100m_locked : std_logic;
-
+ signal clk_100m_s : std_logic;
+ signal clk_100m_fb_s : std_logic;
+ signal clk_100m_locked_s : std_logic;
-- Peripherals on the memory bus
- signal tumbl_out : std_logic_vector(31 downto 0);
- signal tumbl_ta : std_logic;
- signal tumbl_ce : std_logic;
-
- signal irc_reg_out : std_logic_vector(31 downto 0);
- signal irc_reg_ta : std_logic;
- signal irc_reg_ce : std_logic;
-
- signal calib_out : std_logic_vector(31 downto 0);
- signal calib_ta : std_logic;
- signal calib_ce : std_logic;
-
+ signal tumbl_out_s : std_logic_vector(31 downto 0);
+ signal tumbl_ta_s : std_logic;
+ signal tumbl_ce_s : std_logic;
+ --
+ signal irc_reg_out_s : std_logic_vector(31 downto 0);
+ signal irc_reg_ta_s : std_logic;
+ signal irc_reg_ce_s : std_logic;
+ --
+ signal calib_out_s : std_logic_vector(31 downto 0);
+ signal calib_ta_s : std_logic;
+ signal calib_ce_s : std_logic;
-- Signals for external bus transmission
- signal data_in_bus : std_logic_vector(31 downto 0);
- signal data_out_bus : std_logic_vector(31 downto 0);
-
+ signal data_i_s : std_logic_vector(31 downto 0);
+ signal data_o_s : std_logic_vector(31 downto 0);
-- Signals for internal transaction
- signal last_address : std_logic_vector(15 downto 0);
- signal last_rd : std_logic;
- signal last_bls : std_logic_vector(3 downto 0);
+ signal last_address_s : std_logic_vector(15 downto 0);
+ signal last_rd_s : std_logic;
+ signal last_bls_s : std_logic_vector(3 downto 0);
-- Reading logic:
-- Broadcast rd only till ta (transaction acknowledge)
-- Data latching is synchronous - it's purpose is to
-- provide stable data for CPU on the bus on high rise
-- of trans. ack signal
- signal rd_f : std_logic;
- signal rd_d : std_logic;
-
- signal data_read : std_logic_vector(31 downto 0);
-
- signal i_ta : std_logic;
- signal i_rd : std_logic;
- signal acked : std_logic;
+ signal rd_f_s : std_logic; -- Filtered RD
+ signal rd_d_s : std_logic; -- D over RD
+ signal i_ta_s : std_logic; -- Internal bus TA (active 1)
+ signal i_rd_s : std_logic; -- Internal bus RD (active 1)
+ --
+ signal data_read_s : std_logic_vector(31 downto 0); -- Latched read data
+ --
+ signal acked_s : std_logic;
-- Writing logic:
- signal bls_f : std_logic_vector(3 downto 0);
- signal bls_d : std_logic_vector(3 downto 0);
-
- signal data_write : std_logic_vector(31 downto 0);
-
- signal i_bls : std_logic_vector(3 downto 0);
+ signal bls_f_s : std_logic_vector(3 downto 0); -- Filtered BLS
+ signal bls_d_s : std_logic_vector(3 downto 0); -- D over BLS
+ signal i_bls_s : std_logic_vector(3 downto 0); -- Internal BLS (active 1)
+ --
+ signal data_write_s : std_logic_vector(31 downto 0); -- Data broadcasted to write
begin
clk_100m_dcm_sp : DCM_SP
generic map
(
- clkdv_divide => 2.0,
- clkfx_divide => 1,
- clkfx_multiply => 2,
- clkin_divide_by_2 => false,
- clkin_period => 20.0, -- 50 MHz
- clkout_phase_shift => "NONE",
- clk_feedback => "1X",
- deskew_adjust => "SYSTEM_SYNCHRONOUS",
- dfs_frequency_mode => "LOW",
- dll_frequency_mode => "LOW",
- dss_mode => "NONE",
+ clkdv_divide => 2.0,
+ clkfx_divide => 1,
+ clkfx_multiply => 2,
+ clkin_divide_by_2 => false,
+ clkin_period => 20.0, -- 50 MHz
+ clkout_phase_shift => "NONE",
+ clk_feedback => "1X",
+ deskew_adjust => "SYSTEM_SYNCHRONOUS",
+ dfs_frequency_mode => "LOW",
+ dll_frequency_mode => "LOW",
+ dss_mode => "NONE",
duty_cycle_correction => true,
- factory_jf => X"c080",
- phase_shift => 0,
- startup_wait => false
+ factory_jf => X"c080",
+ phase_shift => 0,
+ startup_wait => false
)
port map
(
- clk0 => clk_100m_fb,
- clk180 => open,
- clk270 => open,
- clk2x => clk_100m,
- clk2x180 => open,
- clk90 => open,
- clkdv => open,
- clkfx => open,
- clkfx180 => open,
- locked => clk_100m_locked,
- psdone => open,
- status => open,
- clkfb => clk_100m_fb,
- clkin => clk_50m,
- dssen => '0',
- psclk => '0',
- psen => '0',
- psincdec => '0',
- rst => neg_init
+ clk0 => clk_100m_fb_s,
+ clk180 => open,
+ clk270 => open,
+ clk2x => clk_100m_s,
+ clk2x180 => open,
+ clk90 => open,
+ clkdv => open,
+ clkfx => open,
+ clkfx180 => open,
+ locked => clk_100m_locked_s,
+ psdone => open,
+ status => open,
+ clkfb => clk_100m_fb_s,
+ clkin => clk_50m,
+ dssen => '0',
+ psclk => '0',
+ psen => '0',
+ psincdec => '0',
+ rst => neg_init_s
);
-- IRC interconnect
memory_bus_irc: bus_irc
port map
(
- clk => clk_100m,
- reset => reset,
- address => address(3 downto 0),
- ce => irc_reg_ce,
- data_in => data_in_bus(0),
- data_out => irc_reg_out,
- rd => i_rd,
- wr => i_bls(0),
- ta => irc_reg_ta,
-
- irc1_a => irc1_a,
- irc1_b => irc1_b,
- irc1_index => irc1_index,
- irc1_mark => irc1_mark,
-
- irc2_a => irc2_a,
- irc2_b => irc2_b,
- irc2_index => irc2_index,
- irc2_mark => irc2_mark,
-
- irc3_a => irc3_a,
- irc3_b => irc3_b,
- irc3_index => irc3_index,
- irc3_mark => irc3_mark,
-
- irc4_a => irc4_a,
- irc4_b => irc4_b,
- irc4_index => irc4_index,
- irc4_mark => irc4_mark
+ clk_i => clk_100m_s,
+ reset_i => reset_s,
+ address_i => address(3 downto 0),
+ ce_i => irc_reg_ce_s,
+ data_i => data_i_s(0),
+ data_o => irc_reg_out_s,
+ rd_i => i_rd_s,
+ wr_i => i_bls_s(0),
+ ta_o => irc_reg_ta_s,
+ --
+ irc1_a_i => irc1_a,
+ irc1_b_i => irc1_b,
+ irc1_index_i => irc1_index,
+ irc1_mark_i => irc1_mark,
+ --
+ irc2_a_i => irc2_a,
+ irc2_b_i => irc2_b,
+ irc2_index_i => irc2_index,
+ irc2_mark_i => irc2_mark,
+ --
+ irc3_a_i => irc3_a,
+ irc3_b_i => irc3_b,
+ irc3_index_i => irc3_index,
+ irc3_mark_i => irc3_mark,
+ --
+ irc4_a_i => irc4_a,
+ irc4_b_i => irc4_b,
+ irc4_index_i => irc4_index,
+ irc4_mark_i => irc4_mark
);
-- Tumbl coprocessor
memory_bus_tumbl: bus_tumbl
port map
(
- clk_100m => clk_100m,
- clk_50m => clk_50m,
- reset => reset,
- ce => tumbl_ce,
- ta => tumbl_ta,
- rd => i_rd,
- bls => i_bls,
- address => address(11 downto 0),
- data_in => data_in_bus,
- data_out => tumbl_out,
-
- XMEMB_o => open,
- XMEMB_i.clken => '1',
- XMEMB_i.data => (others => '1'),
- XMEMB_i.int => '0',
- XMEMB_sel_o => open
+ clk_100m_i => clk_100m_s,
+ clk_50m_i => clk_50m,
+ reset_100m_i => reset_s,
+ ce_100m_i => tumbl_ce_s,
+ ta_100m_o => tumbl_ta_s,
+ rd_100m_i => i_rd_s,
+ bls_100m_i => i_bls_s,
+ address_100m_i => address(11 downto 0),
+ data_100m_i => data_i_s,
+ data_100m_o => tumbl_out_s,
+ --
+ XMEMB_50m_o => open,
+ XMEMB_50m_i.clken => '1',
+ XMEMB_50m_i.data => (others => '1'),
+ XMEMB_50m_i.int => '0',
+ XMEMB_sel_50m_o => open
);
-- Calibration
memory_bus_calibration: bus_calibration
port map
(
- clk => clk_100m,
- reset => reset,
- ce => calib_ce,
- address => address(1 downto 0),
- rd => i_rd,
- bls => i_bls,
- ta => calib_ta,
- data_in => data_in_bus,
- data_out => calib_out
+ clk_i => clk_100m_s,
+ reset_i => reset_s,
+ ce_i => calib_ce_s,
+ address_i => address(1 downto 0),
+ rd_i => i_rd_s,
+ bls_i => i_bls_s,
+ ta_o => calib_ta_s,
+ data_i => data_i_s,
+ data_o => calib_out_s
);
-- Filters
--bls_f <= bls when bls = bls_d else "1111";
- bls_f(0) <= bls(0) when bls(0) = bls_d(0) else '1';
- bls_f(1) <= bls(2) when bls(2) = bls_d(2) else '1';
- bls_f(2) <= bls(2) when bls(2) = bls_d(2) else '1';
- bls_f(3) <= bls(3) when bls(3) = bls_d(3) else '1';
- rd_f <= rd when rd = rd_d else '1';
+ bls_f_s(0) <= bls(0) when bls(0) = bls_d_s(0) else '1';
+ bls_f_s(1) <= bls(2) when bls(2) = bls_d_s(2) else '1';
+ bls_f_s(2) <= bls(2) when bls(2) = bls_d_s(2) else '1';
+ bls_f_s(3) <= bls(3) when bls(3) = bls_d_s(3) else '1';
+ rd_f_s <= rd when rd = rd_d_s else '1';
-- Bus update
- memory_bus_update: process(clk_100m)
+memory_bus_update:
+ process(clk_100m_s)
begin
- if clk_100m = '1' and clk_100m'event then
+ if clk_100m_s = '1' and clk_100m_s'event then
-- Set every signal to inactive state here
- irc_reg_ce <= '1';
- tumbl_ce <= '1';
- calib_ce <= '1';
- i_rd <= '1';
- i_bls <= (others => '1');
- data_in_bus <= (others => 'X');
+ irc_reg_ce_s <= '0';
+ tumbl_ce_s <= '0';
+ calib_ce_s <= '0';
+ i_rd_s <= '0';
+ i_bls_s <= (others => '0');
+ data_i_s <= (others => 'X');
-- Check if we have chip select
- if cs0_xc = '0' then
+ if reset_s = '1' then
+ acked_s <= '1';
+ i_ta_s <= '0';
+ data_read_s <= (others => '0');
+ elsif cs0_xc = '0' then
-- Memory Map (16-bit address @ 32-bit each)
-- 0x8000 - 0x800F: IRC registers
-- 0xFFFC - 0xFFFF: Calibration
- if address < "0001000000000000" then -- Tumbl
- tumbl_ce <= '0';
- i_ta <= tumbl_ta;
- data_out_bus <= tumbl_out;
- elsif address(15 downto 4) = "100000000000" then -- IRC
- irc_reg_ce <= '0';
- i_ta <= irc_reg_ta;
- data_out_bus <= irc_reg_out;
+ if address < "0001000000000000" then -- Tumbl
+ tumbl_ce_s <= '1';
+ i_ta_s <= tumbl_ta_s;
+ data_o_s <= tumbl_out_s;
+ elsif address(15 downto 4) = "100000000000" then -- IRC
+ irc_reg_ce_s <= '1';
+ i_ta_s <= irc_reg_ta_s;
+ data_o_s <= irc_reg_out_s;
elsif address(15 downto 2) = "11111111111111" then -- Calibration
- calib_ce <= '0';
- i_ta <= calib_ta;
- data_out_bus <= calib_out;
+ calib_ce_s <= '1';
+ i_ta_s <= calib_ta_s;
+ data_o_s <= calib_out_s;
end if;
-- Reading
- if rd_f = '0' then
- if last_rd = '1' or last_address /= address then
+ if rd_f_s = '0' then
+ if last_rd_s = '1' or last_address_s /= address then
-- Getting something new
-- Set internal RD to active and reset ack and latched data
- acked <= '0';
- i_rd <= '0';
+ acked_s <= '0';
+ i_rd_s <= '1';
-- Data latching - synchronous
- data_read <= (others => 'X');
- elsif i_rd = '0' and acked = '0' and i_ta = '0' then
+ data_read_s <= (others => 'X');
+ elsif i_rd_s = '1' and acked_s = '0' and i_ta_s = '1' then
-- Got acknowledge, latch data
- acked <= '1';
- data_read <= data_out_bus;
- elsif acked = '0' then
- -- Ongoing read, keep the signal low
- i_rd <= '0';
- data_read <= (others => 'X');
+ acked_s <= '1';
+ data_read_s <= data_o_s;
+ elsif acked_s = '0' then
+ -- Ongoing read, keep the signal active
+ i_rd_s <= '1';
+ data_read_s <= (others => 'X');
end if;
- last_address <= address;
+ last_address_s <= address;
else
-- Not reading, anything goes
- data_read <= (others => 'X');
+ data_read_s <= (others => 'X');
end if;
- last_rd <= rd_f;
+ last_rd_s <= rd_f_s;
- -- Writing (BLS is filtered due to bus error otherwise)
- if bls_f /= "1111" then
+ -- Writing
+ if bls_f_s /= "1111" then
- if last_bls /= bls_f or last_address /= address then
+ if last_bls_s /= bls_f_s or last_address_s /= address then
-- Broadcast BLS for once cycle to write the data
- i_bls <= bls_f;
- data_in_bus <= data_write;
+ i_bls_s <= not bls_f_s;
+ data_i_s <= data_write_s;
end if;
- last_address <= address;
+ last_address_s <= address;
end if;
- last_bls <= bls_f;
+ last_bls_s <= bls_f_s;
else
-- Set last read / bls to '1' if CS0 is not asserted
- last_rd <= '1';
- last_bls <= (others => '1');
+ last_rd_s <= '1';
+ last_bls_s <= (others => '1');
end if;
-- Filters
- bls_d <= bls;
- rd_d <= rd;
+ bls_d_s <= bls;
+ rd_d_s <= rd;
end if;
-- If RD and BLS is not high, we must keep DATA at high impedance
-- or the FPGA collides with SDRAM (damaging each other)
- memory_bus_out: process(cs0_xc, rd, data, data_read)
+memory_bus_out:
+ process(cs0_xc, rd, data, data_read_s)
begin
-- CS0 / RD / BLS are active LOW
if cs0_xc = '0' and rd = '0' then
- data <= data_read;
+ data <= data_read_s;
else
-- IMPORTANT!!!
data <= (others => 'Z');
end if;
- data_write <= data;
+ data_write_s <= data;
end process;
-- Reset
- initialization: process(init, clk_100m_locked)
+initialization:
+ process(init, clk_100m_locked_s)
begin
- neg_init <= not init;
- reset <= (not init) or (not clk_100m_locked);
+ -- TODO: Proper reset (lacks filter and propagation with ack as we use PLL)
+ neg_init_s <= not init;
+ reset_s <= (not init) or (not clk_100m_locked_s);
end process;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity memory_region is
-end memory_region;
-
-architecture Behavioral of memory_region is
-
-begin
-
-
-end Behavioral;
-
entity qcounter is
port
(
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- index0 : in std_logic;
-
- qcount : out std_logic_vector (31 downto 0);
- qcount_index : out std_logic_vector (31 downto 0);
- a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
- ab_error : out std_logic
+ -- Inputs
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ a0_i, b0_i : in std_logic;
+ index0_i : in std_logic;
+ -- Outputs
+ qcount_o : out std_logic_vector (31 downto 0);
+ qcount_index_o : out std_logic_vector (31 downto 0);
+ a_rise_o, a_fall_o : out std_logic;
+ b_rise_o, b_fall_o : out std_logic;
+ ab_event_o : out std_logic;
+ ab_error_o : out std_logic
);
end qcounter;
architecture behavioral of qcounter is
- signal last_reset: std_logic;
- signal a, b, a_prev, b_prev: std_logic;
- signal index: std_logic;
- signal count_prev: std_logic_vector (29 downto 0);
- signal count: std_logic_vector (29 downto 0);
- signal count_index_prev: std_logic_vector (31 downto 0);
- signal count_index: std_logic_vector (31 downto 0);
+ signal last_reset_s : std_logic;
+ signal a_s, b_s : std_logic;
+ signal a_prev_s, b_prev_s : std_logic;
+ signal index_s : std_logic;
+ signal count_prev_s : std_logic_vector (29 downto 0);
+ signal count_s : std_logic_vector (29 downto 0);
+ signal count_index_prev_s : std_logic_vector (31 downto 0);
+ signal count_index_s : std_logic_vector (31 downto 0);
begin
dff_a: dff2
port map
(
- clk => clk,
- reset => '0',
- d => a0,
- q => a
+ clk_i => clk_i,
+ reset_i => '0',
+ d_i => a0_i,
+ q_o => a_s
);
dff_b: dff2
port map
(
- clk => clk,
- reset => '0',
- d => b0,
- q => b
+ clk_i => clk_i,
+ reset_i => '0',
+ d_i => b0_i,
+ q_o => b_s
);
dff_index: dff2
port map
(
- clk => clk,
- reset => '0',
- d => index0,
- q => index
+ clk_i => clk_i,
+ reset_i => '0',
+ d_i => index0_i,
+ q_o => index_s
);
- qcount(0) <= a xor b;
- qcount(1) <= b;
- qcount(31 downto 2) <= count;
+ qcount_o(0) <= a_s xor b_s;
+ qcount_o(1) <= b_s;
+ qcount_o(31 downto 2) <= count_s;
- qcount_index <= count_index;
+ qcount_index_o <= count_index_s;
- comb_event: process (reset, last_reset, a_prev, b_prev, a, b)
- begin
- a_rise <= '0';
- a_fall <= '0';
- b_rise <= '0';
- b_fall <= '0';
- ab_event <= '0';
- ab_error <= '0';
+comb_event:
+ process (reset_i, last_reset_s, a_prev_s, b_prev_s, a_s, b_s)
+ begin
+ a_rise_o <= '0';
+ a_fall_o <= '0';
+ b_rise_o <= '0';
+ b_fall_o <= '0';
+ ab_event_o <= '0';
+ ab_error_o <= '0';
- if reset = '0' and last_reset = '0' then
- if ((a xor a_prev) and (b xor b_prev)) = '1' then
+ if reset_i = '0' and last_reset_s = '0' then
+ if ((a_s xor a_prev_s) and (b_s xor b_prev_s)) = '1' then
-- forbidden double transition
- ab_error <= '1';
+ ab_error_o <= '1';
else
- a_rise <= (a xor a_prev) and a;
- a_fall <= (a xor a_prev) and not a;
- b_rise <= (b xor b_prev) and b;
- b_fall <= (b xor b_prev) and not b;
- ab_event <= (a xor a_prev) or (b xor b_prev);
+ a_rise_o <= (a_s xor a_prev_s) and a_s;
+ a_fall_o <= (a_s xor a_prev_s) and (not a_s);
+ b_rise_o <= (b_s xor b_prev_s) and b_s;
+ b_fall_o <= (b_s xor b_prev_s) and (not b_s);
+ ab_event_o <= (a_s xor a_prev_s) or (b_s xor b_prev_s);
end if;
end if;
end process;
- comb_count: process (reset, last_reset, a_prev, b_prev, a, b, index, count_prev, count_index_prev)
- begin
- if reset = '1' or last_reset = '1' then
- count <= count_prev;
- count_index <= count_index_prev;
-
- elsif (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
- count <= count_prev + 1;
-
- if index = '1' then
- count_index(0) <= a xor b;
- count_index(1) <= b;
- count_index(31 downto 2) <= count_prev + 1;
+comb_count:
+ process (reset_i, last_reset_s, a_prev_s, b_prev_s, a_s, b_s,
+ index_s, count_prev_s, count_index_prev_s)
+ begin
+ if reset_i = '1' or last_reset_s = '1' then
+ count_s <= count_prev_s;
+ count_index_s <= count_index_prev_s;
+ elsif (a_prev_s = '0') and (b_prev_s = '1') and (a_s = '0') and
+ (b_s = '0') then
+ count_s <= count_prev_s + 1;
+ if index_s = '1' then
+ count_index_s(0) <= a_s xor b_s;
+ count_index_s(1) <= b_s;
+ count_index_s(31 downto 2) <= count_prev_s + 1;
else
- count_index <= count_index_prev;
+ count_index_s <= count_index_prev_s;
end if;
-
- elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
- count <= count_prev - 1;
-
- if index = '1' then
- count_index(0) <= a xor b;
- count_index(1) <= b;
- count_index(31 downto 2) <= count_prev - 1;
+ elsif (a_prev_s = '0') and (b_prev_s = '0') and (a_s = '0') and
+ (b_s = '1') then
+ count_s <= count_prev_s - 1;
+
+ if index_s = '1' then
+ count_index_s(0) <= a_s xor b_s;
+ count_index_s(1) <= b_s;
+ count_index_s(31 downto 2) <= count_prev_s - 1;
else
- count_index <= count_index_prev;
+ count_index_s <= count_index_prev_s;
end if;
-
else
- count <= count_prev;
-
- if index = '1' then
- count_index(0) <= a xor b;
- count_index(1) <= b;
- count_index(31 downto 2) <= count_prev;
+ count_s <= count_prev_s;
+ if index_s = '1' then
+ count_index_s(0) <= a_s xor b_s;
+ count_index_s(1) <= b_s;
+ count_index_s(31 downto 2) <= count_prev_s;
else
- count_index <= count_index_prev;
+ count_index_s <= count_index_prev_s;
end if;
-
end if;
end process;
- seq: process (clk)
- begin
+seq:
+ process (clk_i)
+ begin
-- Reset for qcounter is synchronous and lasts at least one more cycle
-- to prevent hazardous states after releasing it
- if clk = '1' and clk'event then
- if reset = '0' then
- count_prev <= count;
- count_index_prev <= count_index;
+ if clk_i = '1' and clk_i'event then
+ if reset_i = '0' then
+ count_prev_s <= count_s;
+ count_index_prev_s <= count_index_s;
else
- count_prev <= (others => '0');
- count_index_prev <= (others => '0');
+ count_prev_s <= (others => '0');
+ count_index_prev_s <= (others => '0');
end if;
- a_prev <= a;
- b_prev <= b;
- last_reset <= reset;
+ a_prev_s <= a_s;
+ b_prev_s <= b_s;
+ last_reset_s <= reset_i;
end if;
end process;
+++ /dev/null
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-
-ENTITY irc_reader_tb IS
-END irc_reader_tb;
-
-ARCHITECTURE behavior OF irc_reader_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT irc_reader
- PORT(
- clk : IN std_logic;
- reset : IN std_logic;
- a0 : IN std_logic;
- b0 : IN std_logic;
- index0 : IN std_logic;
- mark0 : IN std_logic;
- qcount : OUT std_logic_vector(31 downto 0);
- ab_event : OUT std_logic;
- ab_error : OUT std_logic;
- out_index : OUT std_logic;
- out_mark : OUT std_logic
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal a0 : std_logic := '0';
- signal b0 : std_logic := '0';
- signal index0 : std_logic := '0';
- signal mark0 : std_logic := '0';
-
- --Outputs
- signal qcount : std_logic_vector(31 downto 0);
- signal ab_event : std_logic;
- signal ab_error : std_logic;
- signal out_index : std_logic;
- signal out_mark : std_logic;
-
- -- Clock period definitions
- constant clk_period : time := 20 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: irc_reader PORT MAP (
- clk => clk,
- reset => reset,
- a0 => a0,
- b0 => b0,
- index0 => index0,
- mark0 => mark0,
- qcount => qcount,
- ab_event => ab_event,
- ab_error => ab_error,
- out_index => out_index,
- out_mark => out_mark
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- reset <= '0';
- wait for 100 ns;
- reset <= '1';
-
- wait for clk_period*10;
-
- -- insert stimulus here
-
- wait;
- end process;
-
-END;
+++ /dev/null
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-
-ENTITY irc_region_tb IS
-END irc_region_tb;
-
-ARCHITECTURE behavior OF irc_region_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT irc_region
- PORT(
- clk : IN std_logic;
- reset : IN std_logic;
- address : IN std_logic_vector(3 downto 0);
- ce : IN std_logic;
- data_in : IN std_logic;
- data_out : OUT std_logic_vector(31 downto 0);
- rd : IN std_logic;
- ta : OUT std_logic;
- wr : IN std_logic;
- irc1_a : IN std_logic;
- irc1_b : IN std_logic;
- irc1_index : IN std_logic;
- irc1_mark : IN std_logic;
- irc2_a : IN std_logic;
- irc2_b : IN std_logic;
- irc2_index : IN std_logic;
- irc2_mark : IN std_logic;
- irc3_a : IN std_logic;
- irc3_b : IN std_logic;
- irc3_index : IN std_logic;
- irc3_mark : IN std_logic;
- irc4_a : IN std_logic;
- irc4_b : IN std_logic;
- irc4_index : IN std_logic;
- irc4_mark : IN std_logic
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal address : std_logic_vector(3 downto 0) := (others => '0');
- signal ce : std_logic := '1';
- signal data_in : std_logic := '0';
- signal rd : std_logic := '1';
- signal wr : std_logic := '1';
- signal irc1_a : std_logic := '0';
- signal irc1_b : std_logic := '0';
- signal irc1_index : std_logic := '0';
- signal irc1_mark : std_logic := '0';
- signal irc2_a : std_logic := '0';
- signal irc2_b : std_logic := '0';
- signal irc2_index : std_logic := '0';
- signal irc2_mark : std_logic := '0';
- signal irc3_a : std_logic := '0';
- signal irc3_b : std_logic := '0';
- signal irc3_index : std_logic := '0';
- signal irc3_mark : std_logic := '0';
- signal irc4_a : std_logic := '0';
- signal irc4_b : std_logic := '0';
- signal irc4_index : std_logic := '0';
- signal irc4_mark : std_logic := '0';
-
- --Outputs
- signal data_out : std_logic_vector(31 downto 0);
- signal ta : std_logic;
-
- -- Clock period definitions
- constant clk_period : time := 20 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: irc_region PORT MAP (
- clk => clk,
- reset => reset,
- address => address,
- ce => ce,
- data_in => data_in,
- data_out => data_out,
- rd => rd,
- ta => ta,
- wr => wr,
- irc1_a => irc1_a,
- irc1_b => irc1_b,
- irc1_index => irc1_index,
- irc1_mark => irc1_mark,
- irc2_a => irc2_a,
- irc2_b => irc2_b,
- irc2_index => irc2_index,
- irc2_mark => irc2_mark,
- irc3_a => irc3_a,
- irc3_b => irc3_b,
- irc3_index => irc3_index,
- irc3_mark => irc3_mark,
- irc4_a => irc4_a,
- irc4_b => irc4_b,
- irc4_index => irc4_index,
- irc4_mark => irc4_mark
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- reset <= '0';
- wait for 100 ns;
- reset <= '1';
-
- wait for clk_period*10;
-
- -- insert stimulus here
-
- -- Set some values to the IRC
- irc1_a <= '1';
- irc1_b <= '1';
-
- irc2_a <= '1';
- irc3_a <= '1';
- irc4_a <= '1';
- wait for clk_period;
-
- irc1_b <= '0';
- irc2_b <= '1';
- irc3_b <= '1';
- irc4_b <= '1';
- wait for clk_period;
-
- irc3_a <= '0';
- irc4_a <= '0';
- wait for clk_period;
-
- irc3_index <= '1';
- wait for clk_period/2;
-
- irc4_b <= '1';
- wait for clk_period/2;
-
- irc3_index <= '0';
- wait for clk_period;
-
- -- Try to read something
-
- -- IRC1 - value
- ce <= '0';
- rd <= '0';
- address <= "0000";
- wait for clk_period*2;
-
- ce <= '1';
- rd <= '1';
- wait for clk_period;
-
- -- IRC1 - state
- ce <= '0';
- rd <= '0';
- address <= "0010";
- wait for clk_period*2;
-
- ce <= '1';
- rd <= '1';
- wait for clk_period;
-
- -- IRC3 - index value
- ce <= '0';
- rd <= '0';
- address <= "1001";
- wait for clk_period*2;
-
- ce <= '1';
- rd <= '1';
- wait for clk_period;
-
- -- Try to write something (reset IRC1 error)
- ce <= '0';
- wr <= '0';
- address <= "0010";
- data_in <= '0';
- wait for clk_period*2;
-
- ce <= '1';
- wr <= '1';
- wait for clk_period;
-
- -- Read it again
- ce <= '0';
- rd <= '0';
- address <= "0010";
- wait for clk_period*2;
-
- ce <= '1';
- rd <= '1';
- wait for clk_period;
-
- wait;
- end process;
-
-END;
+++ /dev/null
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-
-ENTITY irc_register_tb IS
-END irc_register_tb;
-
-ARCHITECTURE behavior OF irc_register_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT irc_register
- PORT(
- clk : IN std_logic;
- reset : IN std_logic;
- a0 : IN std_logic;
- b0 : IN std_logic;
- index0 : IN std_logic;
- mark0 : IN std_logic;
- data_in : IN std_logic;
- data_out : OUT std_logic_vector(31 downto 0);
- ce : IN std_logic_vector(1 downto 0);
- rd : IN std_logic;
- ta : OUT std_logic;
- wr : IN std_logic
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal a0 : std_logic := '0';
- signal b0 : std_logic := '0';
- signal index0 : std_logic := '0';
- signal mark0 : std_logic := '0';
- signal data_in : std_logic := '0';
- signal ce : std_logic_vector(1 downto 0) := (others => '1');
- signal rd : std_logic := '1';
- signal wr : std_logic := '1';
-
- --Outputs
- signal data_out : std_logic_vector(31 downto 0);
- signal ta : std_logic;
-
- -- Clock period definitions
- constant clk_period : time := 20 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: irc_register PORT MAP (
- clk => clk,
- reset => reset,
- a0 => a0,
- b0 => b0,
- index0 => index0,
- mark0 => mark0,
- data_in => data_in,
- data_out => data_out,
- ce => ce,
- rd => rd,
- ta => ta,
- wr => wr
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- reset <= '0';
- wait for 100 ns;
- reset <= '1';
-
- wait for clk_period*10;
-
- -- insert stimulus here
-
- wait;
- end process;
-
-END;
+++ /dev/null
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-
-ENTITY qcounter_tb IS
-END qcounter_tb;
-
-ARCHITECTURE behavior OF qcounter_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT qcounter
- PORT(
- clk : IN std_logic;
- reset : IN std_logic;
- a0 : IN std_logic;
- b0 : IN std_logic;
- qcount : OUT std_logic_vector(31 downto 0);
- a_rise : OUT std_logic;
- a_fall : OUT std_logic;
- b_rise : OUT std_logic;
- b_fall : OUT std_logic;
- ab_event : OUT std_logic;
- ab_error : OUT std_logic
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk : std_logic := '0';
- signal reset : std_logic := '1';
- signal a0 : std_logic := '0';
- signal b0 : std_logic := '0';
-
- --Outputs
- signal qcount : std_logic_vector(31 downto 0);
- signal a_rise : std_logic;
- signal a_fall : std_logic;
- signal b_rise : std_logic;
- signal b_fall : std_logic;
- signal ab_event : std_logic;
- signal ab_error : std_logic;
-
- -- Clock period definitions
- constant clk_period : time := 20 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: qcounter PORT MAP (
- clk => clk,
- reset => reset,
- a0 => a0,
- b0 => b0,
- qcount => qcount,
- a_rise => a_rise,
- a_fall => a_fall,
- b_rise => b_rise,
- b_fall => b_fall,
- ab_event => ab_event,
- ab_error => ab_error
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- reset <= '0';
- wait for 100 ns;
- reset <= '1';
-
- wait for clk_period*10;
-
- -- insert stimulus here
-
- wait;
- end process;
-
-END;
-Subproject commit b4ac16f8af94e83dcf1af5caf7b54a9335f41dd1
+Subproject commit d5b585f31816dac12117f828b2c06f2fdefd092d
projects / fpga / lx-cpu1 / lx-rocon.git / commitdiff