]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-rocon.git/blob - hw/calibration_read_register.vhd
Major refactorization in hw
[fpga/lx-cpu1/lx-rocon.git] / hw / calibration_read_register.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
5 use ieee.numeric_std.all;
6
7 -- Calibration read register - returns fixed value
8 -- Uses clock for writing the ID to the bus
9
10 entity calibration_read_register is
11   generic
12         (
13                 id_g   : std_logic_vector(31 downto 0) := (others => '0')
14         );
15         port
16         (
17                 -- Data bus (read only)
18                 data_o : out std_logic_vector(31 downto 0);
19                 -- Bus signals
20                 rd_i   : in std_logic;
21                 ta_o   : out std_logic
22         );
23 end calibration_read_register;
24
25 architecture Behavioral of calibration_read_register is
26 begin
27
28 memory_bus:
29         process(rd_i)
30         begin
31                 ta_o     <= rd_i;
32                 data_o   <= id_g;
33         end process;
34
35 end Behavioral;