Add registers to LX Master MOSI and SYNC signals to ensure right timing.

[fpga/lx-cpu1/lx-rocon.git] / .gitmodules

diff --git a/.gitmodules b/.gitmodules
index c6a7a3d3b1a4a138d6183e1d3f2de24f9cadcb70..58a36f47b51763bf313ac591cf38fe5bb20a6bfb 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,3 +10,12 @@
 [submodule "submodule/ulan-app"]
        path = submodule/ulan-app
        url = git://git.code.sf.net/p/ulan/ulan-app
+[submodule "submodule/ulan-libs4c"]
+       path = submodule/ulan-libs4c
+       url = git://git.code.sf.net/p/ulan/ulan-libs4c
+[submodule "submodule/ulan-drv"]
+       path = submodule/ulan-drv
+       url = git://git.code.sf.net/p/ulan/ulan-drv
+[submodule "submodule/tumbl"]
+       path = submodule/tumbl
+       url = ssh://git@rtime.felk.cvut.cz/fpga/lx-cpu1/tumbl.git