PXMC: new function pxmc_axis_release added to distinguish between set zero output...

[fpga/lx-cpu1/lx-rocon.git] / sw / app / rocon / appl_pxmc.c

diff --git a/sw/app/rocon/appl_pxmc.c b/sw/app/rocon/appl_pxmc.c
index a7abedc1e86080da736250433f776388674a59d3..8d583a0025dfcdd90bd0cdc322ebae638cb69449 100644 (file)
--- a/sw/app/rocon/appl_pxmc.c
+++ b/sw/app/rocon/appl_pxmc.c
@@ -66,6 +66,7 @@ unsigned pxmc_rocon_pwm_magnitude = PXMC_LXPWR_PWM_CYCLE;
 
 long pxmc_rocon_irc_offset[PXML_MAIN_CNT];
 unsigned pxmc_rocon_mark_filt[PXML_MAIN_CNT];
+unsigned pxmc_rocon_lxpwr_chips = 0;
 
 static inline
 pxmc_rocon_state_t *pxmc_state2rocon_state(pxmc_state_t *mcs)
@@ -135,6 +136,27 @@ void pxmc_rocon_rx_done_sqn_compute(void)
   pxmc_rocon_rx_done_sqn_missoffs = sqn_offs;
 }
 
+uint32_t pxmc_rocon_rx_err_cnt_last;
+uint32_t pxmc_rocon_rx_err_level;
+uint32_t pxmc_rocon_mcc_rx_done_sqn_last;
+uint32_t pxmc_rocon_mcc_stuck;
+
+static inline
+void pxmc_rocon_rx_error_check(void)
+{
+  uint32_t cnt;
+  uint32_t mcc_sqn;
+  pxmcc_data_t *mcc_data = pxmc_rocon_mcc_data();
+
+  cnt = mcc_data->common.rx_err_cnt;
+  pxmc_rocon_rx_err_level = cnt - pxmc_rocon_rx_err_cnt_last;
+  pxmc_rocon_rx_err_cnt_last = cnt;
+
+  mcc_sqn = mcc_data->common.rx_done_sqn;
+  pxmc_rocon_mcc_stuck = mcc_sqn == pxmc_rocon_mcc_rx_done_sqn_last? 1: 0;
+  pxmc_rocon_mcc_rx_done_sqn_last = mcc_sqn;
+}
+
 const uint8_t onesin10bits[1024]={
   0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,
   1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,
@@ -992,6 +1014,11 @@ pxmc_pxmcc_pwm3ph_out(pxmc_state_t *mcs)
 
       pxmcc_cur_ctrl_pi(&pwm_d, &mcsrc->cur_d_err_sum, cur_d_err,
                       mcsrc->cur_d_p, mcsrc->cur_d_i, max_pwm);
+
+      if (pxmc_rocon_rx_err_level >= 2)
+        pxmc_set_errno(mcs, PXMS_E_WINDCURADC);
+      else if (pxmc_rocon_mcc_stuck)
+        pxmc_set_errno(mcs, PXMS_E_MCC_FAULT);
     }
 
     pxmcc_axis_pwm_dq_out(mcs, pwm_d, pwm_q);
@@ -1051,6 +1078,11 @@ pxmc_pxmcc_pwm2ph_out(pxmc_state_t *mcs)
 
       pxmcc_cur_ctrl_pi(&pwm_d, &mcsrc->cur_d_err_sum, cur_d_err,
                       mcsrc->cur_d_p, mcsrc->cur_d_i, max_pwm);
+
+      if (pxmc_rocon_rx_err_level >= 2)
+        pxmc_set_errno(mcs, PXMS_E_WINDCURADC);
+      else if (pxmc_rocon_mcc_stuck)
+        pxmc_set_errno(mcs, PXMS_E_MCC_FAULT);
     }
 
     pwm_q = (pxmc_rocon_pwm_magnitude * ene) >> 15;
@@ -1150,6 +1182,11 @@ pxmc_pxmcc_nofb2ph_out(pxmc_state_t *mcs)
 
     mcc_axis->steps_sqn_next = pxmc_rocon_rx_done_sqn +
                                pxmc_rocon_rx_done_sqn_inc - 1;
+
+    if (pxmc_rocon_rx_err_level >= 2)
+      pxmc_set_errno(mcs, PXMS_E_WINDCURADC);
+    else if (pxmc_rocon_mcc_stuck)
+      pxmc_set_errno(mcs, PXMS_E_MCC_FAULT);
   }
 
   return 0;
@@ -1285,6 +1322,7 @@ IRQ_HANDLER_FNC(pxmc_rocon_rx_done_isr)
 
     pxmc_rocon_rx_done_sqn_compute();
     pxmc_rocon_vin_compute();
+    pxmc_rocon_rx_error_check();
 
     if (pxmc_rocon_rx_data_hist_buff >= pxmc_rocon_rx_data_hist_buff_end)
       pxmc_rocon_rx_data_hist_buff = NULL;
@@ -1368,22 +1406,21 @@ pxmc_rocon_rx_done_isr_setup(irq_handler_t rx_done_isr_handler)
 }
 
 int
-pxmc_rocon_pwm_master_init(void)
+pxmc_rocon_pwm_master_setup(unsigned lxpwr_chips)
 {
   int i;
   int grp_in = 0;
   int grp_out = 0;
   unsigned word_slot;
   unsigned receiver_done_div = 1;
+  unsigned lxpwr_chips_max = 2;
  #ifdef LXPWR_WITH_SIROLADC
   unsigned lxpwr_header = 1;
   unsigned lxpwr_words = 1 + 8 * 2 + 2;
-  unsigned lxpwr_chips = 2;
   unsigned lxpwr_chip_pwm_cnt = 8;
  #else /*LXPWR_WITH_SIROLADC*/
   unsigned lxpwr_header = 0;
   unsigned lxpwr_words = 8;
-  unsigned lxpwr_chips = 2;
   unsigned lxpwr_chip_pwm_cnt = 8;
  #endif /*LXPWR_WITH_SIROLADC*/
 
@@ -1397,14 +1434,23 @@ pxmc_rocon_pwm_master_init(void)
   *fpga_lx_master_receiver_done_div = receiver_done_div << 8;
   pxmc_rocon_rx_done_sqn_inc = receiver_done_div;
 
-  for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips; i++)
+  if (lxpwr_chips > lxpwr_chips_max)
+    return -1;
+
+  for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips_max; i++)
     fpga_lx_master_receiver_base[i] = 0;
 
+  if (lxpwr_chips >= 2) {
+    word_slot = LX_MASTER_DATA_OFFS + lxpwr_words;
+    fpga_lx_master_receiver_base[grp_in++] = (word_slot << 8) | lxpwr_words;
+  }
+
   word_slot = LX_MASTER_DATA_OFFS;
   fpga_lx_master_receiver_base[grp_in++] = (word_slot << 8) | lxpwr_words;
+
   fpga_lx_master_receiver_base[grp_in++] = 0x0000;
 
-  for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips; i++)
+  for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips_max; i++)
     fpga_lx_master_transmitter_base[i] = 0;
 
   word_slot = LX_MASTER_DATA_OFFS + lxpwr_header + lxpwr_chip_pwm_cnt;
@@ -1428,6 +1474,76 @@ pxmc_rocon_pwm_master_init(void)
   return 0;
 }
 
+int
+pxmc_rocon_wait_rx_done(void)
+{
+  uint32_t sqn_last;
+  uint32_t sqn_act;
+  uint32_t timeout = 10000;
+
+  sqn_last = *fpga_lx_master_receiver_done_div;
+  sqn_last = sqn_last & 0x1f;
+
+  do {
+    sqn_act = *fpga_lx_master_receiver_done_div;
+    sqn_act = sqn_act & 0x1f;
+    if (sqn_act != sqn_last)
+      return 0;
+  } while(timeout--);
+
+  return -1;
+}
+
+int
+pxmc_rocon_pwm_master_init(void)
+{
+  int res;
+  volatile uint32_t *lxpwr_header_ptr;
+  unsigned lxpwr_words = 1 + 8 * 2 + 2;
+
+  pxmc_rocon_lxpwr_chips = 0;
+
+  res = pxmc_rocon_pwm_master_setup(2);
+  if (res < 0)
+    return 0;
+
+  if (pxmc_rocon_wait_rx_done() < 0)
+    return -1;
+  if (pxmc_rocon_wait_rx_done() < 0)
+    return -1;
+
+  lxpwr_header_ptr = fpga_lx_master_receiver_base;
+  lxpwr_header_ptr += LX_MASTER_DATA_OFFS;
+
+  if (lxpwr_header_ptr[0] == 0xb100 + lxpwr_words - 1) {
+    if (lxpwr_header_ptr[lxpwr_words] == 0xb100 + lxpwr_words - 1) {
+      pxmc_rocon_lxpwr_chips = 2;
+      return 2;
+    }
+    return -1;
+  }
+
+  if (lxpwr_header_ptr[lxpwr_words] != 0xb100 + lxpwr_words - 1) {
+    return -1;
+  }
+
+  res = pxmc_rocon_pwm_master_setup(1);
+  if (res < 0)
+    return 0;
+
+  if (pxmc_rocon_wait_rx_done() < 0)
+    return -1;
+  if (pxmc_rocon_wait_rx_done() < 0)
+    return -1;
+
+  if (lxpwr_header_ptr[0] != 0xb100 + lxpwr_words - 1)
+    return -1;
+
+  pxmc_rocon_lxpwr_chips = 1;
+
+  return 1;
+}
+
 int pxmc_ptofs_from_index(pxmc_state_t *mcs, unsigned long irc,
                            unsigned long index_irc, int diff2err)
 {
@@ -2248,7 +2364,7 @@ pxmc_axis_mode(pxmc_state_t *mcs, int mode)
   int res;
   int prev_mode;
 
-  pxmc_set_const_out(mcs, 0);
+  pxmc_axis_release(mcs);
   pxmc_clear_flag(mcs, PXMS_ENI_b);
   pxmc_clear_flags(mcs,PXMS_ENO_m);
   /* Clear possible stall index flags from hardware */
@@ -2267,7 +2383,8 @@ pxmc_axis_mode(pxmc_state_t *mcs, int mode)
     mode = PXMC_AXIS_MODE_DC;
 
   if ((prev_mode == PXMC_AXIS_MODE_BLDC_PXMCC) ||
-      (prev_mode == PXMCC_MODE_STEPPER_WITH_IRC))
+      (prev_mode == PXMC_AXIS_MODE_STEPPER_WITH_IRC_PXMCC) ||
+      (prev_mode == PXMC_AXIS_MODE_STEPPER_PXMCC))
     pxmcc_axis_setup(mcs, PXMCC_MODE_IDLE);
 
   res = pxmc_axis_pt4mode(mcs, mode);
@@ -2394,7 +2511,7 @@ int pxmc_done(void)
 
   pxmc_for_each_mcs(var, mcs)
   {
-    pxmc_set_const_out(mcs,0);
+    pxmc_axis_release(mcs);
   }
 
   pxmc_main_list.pxml_cnt = 0;
@@ -2408,6 +2525,13 @@ int pxmc_initialize(void)
   int res;
   int i;
 
+  pxmc_main_list.pxml_cnt = 0;
+  pxmc_dbg_hist = NULL;
+ #ifdef PXMC_ROCON_TIMED_BY_RX_DONE
+  disable_irq(ROCON_RX_IRQn);
+ #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/
+  __memory_barrier();
+
   pxmc_state_t *mcs = &mcs0.base;
   lpc_qei_state_t *qst = &lpc_qei_state;
 
@@ -2433,13 +2557,14 @@ int pxmc_initialize(void)
   /*pxmc_ctm4pwm3f_wr(mcs, 0, 0, 0);*/
   //pxmc_rocon_pwm3ph_wr(mcs, 0, 0, 0);
 
-  pxmc_rocon_pwm_master_init();
+  res = pxmc_rocon_pwm_master_init();
+  if (res < 0)
+    return -1;
+
  #ifdef PXMC_ROCON_TIMED_BY_RX_DONE
   pxmc_rocon_rx_done_isr_setup(pxmc_rocon_rx_done_isr);
  #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/
 
-  pxmc_main_list.pxml_cnt = 0;
-  pxmc_dbg_hist = NULL;
   __memory_barrier();
   pxmc_main_list.pxml_cnt = PXML_MAIN_CNT;