hw/lx_rocon_top.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6
   7 library unisim;
   8 use unisim.vcomponents.all;
   9
  10 use work.mbl_pkg.all;
  11 use work.lx_rocon_pkg.all;
  12
  13 -- lx_rocon_top - wires the modules with the outside world
  14
  15 -- ======================================================
  16 --  MASTER CPU EXTERNAL MEMORY BUS
  17 -- ======================================================
  18 --
  19 -- Master cpu memory bus has the following wires:
  20 --
  21 -- - address[15..0]          The address, used to mark chip enable
  22 -- - data_in[31..0]          The data coming to bus
  23 -- - data_out[31..0]         The data coming from bus, multiplexed
  24 -- - bls[3..0]               Write enable for respective bytes
  25
  26 entity lx_rocon_top is
  27         port
  28         (
  29                 -- External
  30                 --clk_cpu     : in std_logic;
  31                 clk_50m     : in std_logic;
  32                 --
  33                 cs0_xc      : in std_logic;
  34                 --
  35                 rd          : in std_logic;
  36                 bls         : in std_logic_vector(3 downto 0);
  37                 address     : in std_logic_vector(15 downto 0);
  38                 data        : inout std_logic_vector(31 downto 0);
  39                 --
  40                 irc0_a      : in std_logic;
  41                 irc0_b      : in std_logic;
  42                 irc0_index  : in std_logic;
  43                 irc0_mark   : in std_logic;
  44                 --
  45                 irc1_a      : in std_logic;
  46                 irc1_b      : in std_logic;
  47                 irc1_index  : in std_logic;
  48                 irc1_mark   : in std_logic;
  49                 --
  50                 irc2_a      : in std_logic;
  51                 irc2_b      : in std_logic;
  52                 irc2_index  : in std_logic;
  53                 irc2_mark   : in std_logic;
  54                 --
  55                 irc3_a      : in std_logic;
  56                 irc3_b      : in std_logic;
  57                 irc3_index  : in std_logic;
  58                 irc3_mark   : in std_logic;
  59                 --
  60                 irc4_a      : in std_logic;
  61                 irc4_b      : in std_logic;
  62                 irc4_index  : in std_logic;
  63                 irc4_mark   : in std_logic;
  64                 --
  65                 irc5_a      : in std_logic;
  66                 irc5_b      : in std_logic;
  67                 irc5_index  : in std_logic;
  68                 irc5_mark   : in std_logic;
  69                 --
  70                 irc6_a      : in std_logic;
  71                 irc6_b      : in std_logic;
  72                 irc6_index  : in std_logic;
  73                 irc6_mark   : in std_logic;
  74                 --
  75                 irc7_a      : in std_logic;
  76                 irc7_b      : in std_logic;
  77                 irc7_index  : in std_logic;
  78                 irc7_mark   : in std_logic;
  79                 --
  80                 init        : in std_logic;
  81                 --
  82                 s1_clk_in   : in std_logic;
  83                 s1_miso     : in std_logic;
  84                 s1_sync_in  : in std_logic;
  85                 --
  86                 s1_clk_out  : out std_logic;
  87                 s1_mosi     : out std_logic;
  88                 s1_sync_out : out std_logic
  89         );
  90 end lx_rocon_top;
  91
  92 architecture Behavioral of lx_rocon_top is
  93
  94         -- Reset signal
  95         signal reset_s                  : std_logic;
  96         signal init_s                   : std_logic;
  97         -- Peripherals on the memory buses
  98         -- Master to Tumbl DMEM / IMEM (Master)
  99         signal tumbl_out_s              : std_logic_vector(31 downto 0);
 100         signal tumbl_ce_s               : std_logic;
 101         -- Measurement (Master)
 102         signal meas_out_s               : std_logic_vector(31 downto 0);
 103         signal meas_ce_s                : std_logic;
 104         -- Master to Tumbl XMEM
 105         signal master_tumbl_xmem_out_s  : std_logic_vector(31 downto 0);
 106         signal master_tumbl_xmem_ce_s   : std_logic;
 107         signal master_tumbl_xmem_lock_s : std_logic;
 108         -- IRC (Tumbl)
 109         signal irc_proc_out_s            : std_logic_vector(31 downto 0);
 110         signal irc_proc_ce_s             : std_logic;
 111         signal irc_proc_next_ce_s        : std_logic;
 112         -- LX Master (Tumbl)
 113         signal lxmaster_out_s           : std_logic_vector(15 downto 0);
 114         signal lxmaster_ce_s            : std_logic;
 115         signal lxmaster_next_ce_s       : std_logic;
 116         -- Signals for external bus transmission
 117         signal data_i_s                 : std_logic_vector(31 downto 0);
 118         signal data_o_s                 : std_logic_vector(31 downto 0);
 119         -- Signals for internal transaction
 120         signal last_address_s           : std_logic_vector(15 downto 0);
 121         signal next_last_address_s      : std_logic_vector(15 downto 0);
 122         signal next_address_hold_s      : std_logic;
 123         signal address_hold_s           : std_logic;
 124         signal last_rd_s                : std_logic;
 125         signal next_last_rd_s           : std_logic;
 126         signal last_bls_s               : std_logic_vector(3 downto 0); -- prev bls_f_s (active 1)
 127         signal next_last_bls_s          : std_logic_vector(3 downto 0);
 128
 129         -- Reading logic for Master CPU:
 130         -- Broadcast rd only till ta (transaction acknowledge)
 131         -- is received, then latch the data till the state of
 132         -- rd or address changes
 133         --
 134         -- Data latching is synchronous - it's purpose is to
 135         -- provide stable data for CPU on the bus
 136         signal cs0_xc_f_s          : std_logic;
 137         signal rd_f_s              : std_logic; -- Filtered RD
 138         signal i_rd_s              : std_logic; -- Internal bus RD (active 1)
 139         signal next_i_rd_s         : std_logic;
 140         signal last_i_rd_s         : std_logic; -- Delayed RD bus, used for latching
 141         signal next_last_i_rd_s    : std_logic;
 142         signal i_rd_cycle2_s       : std_logic; -- Some internal subsystems provide
 143         signal next_i_rd_cycle2_s  : std_logic; -- data only after 2 cycles
 144         --
 145         signal address_f_s         : std_logic_vector(15 downto 0); -- Filtered address
 146         --
 147         signal data_f_s            : std_logic_vector(31 downto 0); -- Filterred input data
 148         --
 149         signal data_read_s         : std_logic_vector(31 downto 0); -- Latched read data
 150         signal next_data_read_s    : std_logic_vector(31 downto 0);
 151
 152         -- Writing logic:
 153         signal bls_f_s             : std_logic_vector(3 downto 0); -- Filtered BLS (active 1)
 154         signal i_bls_s             : std_logic_vector(3 downto 0); -- Internal BLS (active 1)
 155         signal next_i_bls_s        : std_logic_vector(3 downto 0);
 156         --
 157         signal data_write_s        : std_logic_vector(31 downto 0); -- Data broadcasted to write
 158         signal next_data_write_s   : std_logic_vector(31 downto 0);
 159
 160         -- Tumbl:
 161         signal tumbl_bls_s         : std_logic_vector(3 downto 0);
 162         signal tumbl_address_s     : std_logic_vector(14 downto 0);
 163         signal tumbl_data_i_s      : std_logic_vector(31 downto 0);
 164         --
 165         signal tumbl_xmemb_o_s     : CORE2DMEMB_Type;
 166         signal tumbl_xmemb_i_s     : DMEMB2CORE_Type;
 167         signal tumbl_xmemb_sel_s   : std_logic;
 168
 169         -- XST attributes
 170         attribute REGISTER_DUPLICATION : string;
 171         attribute REGISTER_DUPLICATION of rd : signal is "NO";
 172         attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
 173         attribute REGISTER_DUPLICATION of bls : signal is "NO";
 174         attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
 175         attribute REGISTER_DUPLICATION of address : signal is "NO";
 176         attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
 177         attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
 178
 179 begin
 180
 181 -- Tumbl coprocessor
 182 memory_bus_tumbl: bus_tumbl
 183         port map
 184         (
 185                 clk_i          => clk_50m,
 186                 reset_i        => reset_s,
 187                 ce_i           => tumbl_ce_s,
 188                 bls_i          => i_bls_s,
 189                 address_i      => address_f_s(11 downto 0),
 190                 data_i         => data_i_s,
 191                 data_o         => tumbl_out_s,
 192                 --
 193                 xmemb_o        => tumbl_xmemb_o_s,
 194                 xmemb_i        => tumbl_xmemb_i_s,
 195                 xmemb_sel_o    => tumbl_xmemb_sel_s
 196         );
 197
 198 -- Measurement
 199 memory_bus_measurement: bus_measurement
 200         port map
 201         (
 202                 clk_i     => clk_50m,
 203                 reset_i   => reset_s,
 204                 ce_i      => meas_ce_s,
 205                 address_i => address_f_s(1 downto 0),
 206                 bls_i     => i_bls_s,
 207                 data_i    => data_i_s,
 208                 data_o    => meas_out_s
 209         );
 210
 211 -- IRC interconnect
 212 memory_bus_irc: bus_irc
 213         port map
 214         (
 215                 reset_i        => reset_s,
 216                 --
 217                 clk_i          => clk_50m,
 218                 address_i      => tumbl_address_s(4 downto 0),
 219                 next_ce_i      => irc_proc_next_ce_s,
 220                 data_i         => tumbl_data_i_s,
 221                 data_o         => irc_proc_out_s,
 222                 bls_i          => tumbl_bls_s,
 223                 --
 224                 irc_i(0).a     => irc0_a,
 225                 irc_i(0).b     => irc0_b,
 226                 irc_i(0).index => irc0_index,
 227                 irc_i(0).mark  => irc0_mark,
 228                 --
 229                 irc_i(1).a     => irc1_a,
 230                 irc_i(1).b     => irc1_b,
 231                 irc_i(1).index => irc1_index,
 232                 irc_i(1).mark  => irc1_mark,
 233                 --
 234                 irc_i(2).a     => irc2_a,
 235                 irc_i(2).b     => irc2_b,
 236                 irc_i(2).index => irc2_index,
 237                 irc_i(2).mark  => irc2_mark,
 238                 --
 239                 irc_i(3).a     => irc3_a,
 240                 irc_i(3).b     => irc3_b,
 241                 irc_i(3).index => irc3_index,
 242                 irc_i(3).mark  => irc3_mark,
 243                 --
 244                 irc_i(4).a     => irc4_a,
 245                 irc_i(4).b     => irc4_b,
 246                 irc_i(4).index => irc4_index,
 247                 irc_i(4).mark  => irc4_mark,
 248                 --
 249                 irc_i(5).a     => irc5_a,
 250                 irc_i(5).b     => irc5_b,
 251                 irc_i(5).index => irc5_index,
 252                 irc_i(5).mark  => irc5_mark,
 253                 --
 254                 irc_i(6).a     => irc6_a,
 255                 irc_i(6).b     => irc6_b,
 256                 irc_i(6).index => irc6_index,
 257                 irc_i(6).mark  => irc6_mark,
 258                 --
 259                 irc_i(7).a     => irc7_a,
 260                 irc_i(7).b     => irc7_b,
 261                 irc_i(7).index => irc7_index,
 262                 irc_i(7).mark  => irc7_mark
 263         );
 264
 265 -- LX Master
 266 memory_bus_lxmaster: bus_lxmaster
 267         port map
 268         (
 269                 reset_i        => reset_s,
 270                 --
 271                 clk_i          => clk_50m,
 272                 address_i      => tumbl_address_s(10 downto 0),
 273                 next_ce_i      => lxmaster_next_ce_s,
 274                 data_i         => tumbl_data_i_s(15 downto 0),
 275                 data_o         => lxmaster_out_s,
 276                 bls_i          => tumbl_bls_s(1 downto 0),
 277                 --
 278                 clock_i        => s1_clk_in,
 279                 miso_i         => s1_miso,
 280                 sync_i         => s1_sync_in,
 281                 --
 282                 clock_o        => s1_clk_out,
 283                 mosi_o         => s1_mosi,
 284                 sync_o         => s1_sync_out
 285         );
 286
 287 -- Reset
 288 dff_reset: dff2
 289         port map
 290         (
 291                 clk_i   => clk_50m,
 292                 d_i     => init_s,
 293                 q_o     => reset_s
 294         );
 295
 296         -- Reset
 297         init_s          <= not init;
 298
 299         -- Signalling
 300         data_i_s        <= data_write_s;
 301
 302         -- Tumbl
 303         tumbl_bls_s     <= i_bls_s when (master_tumbl_xmem_lock_s = '1')
 304                            else tumbl_xmemb_o_s.bls when (tumbl_xmemb_sel_s = '1')
 305                            else "0000";
 306         tumbl_address_s <= address_f_s(14 downto 0) when (master_tumbl_xmem_lock_s = '1')
 307                            else tumbl_xmemb_o_s.addr when (tumbl_xmemb_sel_s = '1')
 308                            else (others => '0');
 309         tumbl_data_i_s  <= data_i_s when (master_tumbl_xmem_lock_s = '1')
 310                            else tumbl_xmemb_o_s.data when (tumbl_xmemb_sel_s = '1')
 311                            else (others => '0');
 312         --
 313         tumbl_xmemb_i_s.int <= '0'; -- No interrupt
 314         -- Enable clken only when available for Tumbl
 315         tumbl_xmemb_i_s.clken <= not master_tumbl_xmem_lock_s;
 316
 317
 318 -- Bus update
 319 memory_bus_logic:
 320         process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_s, i_rd_cycle2_s, last_i_rd_s,
 321                 bls_f_s, last_bls_s, data_f_s, data_write_s,
 322                 data_o_s, data_read_s, last_address_s, address_f_s)
 323         begin
 324                 -- Defaults
 325                 next_i_rd_s  <= '0';
 326                 next_i_rd_cycle2_s <= '0';
 327                 next_address_hold_s <= '0';
 328
 329                 -- Check if we have chip select
 330                 if cs0_xc_f_s = '1' then
 331
 332                         -- Reading
 333                         if rd_f_s = '1' then
 334                                 -- Internal read
 335                                 if last_rd_s = '0' or (last_address_s /= address_f_s) then
 336                                         next_i_rd_s <= '1';
 337                                         next_i_rd_cycle2_s <= '1';
 338                                 elsif i_rd_cycle2_s = '1' then    -- FIXME it seems that some internal
 339                                         next_i_rd_s <= '1'; -- peripherals demands 2 cycles to read
 340                                 end if;
 341
 342                                 if last_i_rd_s = '1' then
 343                                         -- Latch data we just read - they are valid in this cycle
 344                                         next_data_read_s <= data_o_s;
 345                                 else
 346                                         next_data_read_s <= data_read_s;
 347                                 end if;
 348                         else
 349                         --      -- Not reading, anything goes
 350                         --      data_read_s       <= (others => 'X');
 351                                 next_data_read_s  <= data_read_s;
 352                         end if;
 353
 354                         next_last_rd_s            <= rd_f_s;
 355                         next_last_i_rd_s          <= i_rd_s;
 356
 357                         -- Data for write are captured only when BLS signals are stable
 358                         if bls_f_s /= "0000" then
 359                                 next_data_write_s <= data_f_s;
 360                                 next_address_hold_s <= '1';
 361                         else
 362                                 next_data_write_s <= data_write_s;
 363                         end if;
 364
 365                         if (bls_f_s /= "0000") or (rd_f_s = '1') then
 366                                 next_last_address_s <= address_f_s;
 367                         else
 368                                 next_last_address_s <= last_address_s;
 369                         end if;
 370                 else
 371                         next_last_rd_s <= '0';
 372                         next_last_i_rd_s <= '0';
 373
 374                         next_i_bls_s <= "0000";
 375                         next_data_write_s <= data_write_s;
 376                         next_data_read_s  <= data_read_s;
 377                         next_last_address_s <= last_address_s;
 378                 end if;
 379
 380                 -- Data for write are captured at/before BLS signals are negated
 381                 -- and actual write cycle takes place exacly after BLS negation
 382                 if ((last_bls_s and not bls_f_s) /= "0000") or
 383                     ((last_bls_s /= "0000") and (cs0_xc_f_s = '0')) then
 384                         next_i_bls_s <= last_bls_s;
 385                         next_last_bls_s   <= "0000";
 386                         next_address_hold_s <= '1';
 387                 else
 388                         next_i_bls_s <= "0000";
 389                         if cs0_xc_f_s = '1' then
 390                                 next_last_bls_s <= bls_f_s;
 391                         else
 392                                 next_last_bls_s <= "0000" ;
 393                         end if;
 394                 end if;
 395
 396         end process;
 397
 398 -- Bus update
 399 memory_bus_update:
 400         process
 401         begin
 402
 403                 wait until clk_50m = '1' and clk_50m'event;
 404
 405                 address_hold_s <= next_address_hold_s;
 406
 407                 -- Synchronized external signals with main clock domain
 408                 cs0_xc_f_s     <= not cs0_xc;
 409                 bls_f_s        <= not bls;
 410                 rd_f_s         <= not rd;
 411                 data_f_s       <= data;
 412                 if address_hold_s = '0' then
 413                         address_f_s <= address;
 414                 else
 415                         address_f_s <= next_last_address_s;
 416                 end if;
 417
 418                 -- Synchronoust state andvance to next period
 419                 last_bls_s     <= next_last_bls_s;
 420                 last_rd_s      <= next_last_rd_s;
 421                 i_bls_s        <= next_i_bls_s;
 422                 i_rd_s         <= next_i_rd_s;
 423                 i_rd_cycle2_s  <= next_i_rd_cycle2_s;
 424                 last_i_rd_s    <= next_last_i_rd_s;
 425                 data_write_s   <= next_data_write_s;
 426                 last_address_s <= next_last_address_s;
 427                 data_read_s    <= next_data_read_s;
 428                 --
 429                 -- ======================================================
 430                 --  TUMBL BUS
 431                 -- ======================================================
 432
 433                 -- Just copy these to their desired next state
 434                 irc_proc_ce_s <= irc_proc_next_ce_s;
 435                 lxmaster_ce_s <= lxmaster_next_ce_s;
 436
 437         end process;
 438
 439 -- Do the actual wiring here
 440 memory_bus_wiring:
 441         process(cs0_xc_f_s, i_bls_s, address_f_s, tumbl_out_s, meas_out_s, master_tumbl_xmem_out_s)
 442         begin
 443
 444                 -- Inactive by default
 445                 tumbl_ce_s             <= '0';
 446                 meas_ce_s              <= '0';
 447                 master_tumbl_xmem_ce_s <= '0';
 448                 data_o_s               <= (others => '0');
 449
 450                 if cs0_xc_f_s = '1' or i_bls_s /= "0000" then
 451
 452                         -- Memory Map (16-bit address @ 32-bit each)
 453
 454                         -- Each address is seen as 32-bit entry now
 455                         -- 0x0000 - 0x0FFF: Tumbl IMEM / DMEM
 456                         -- 0x1FFC - 0x1FFF: Measurement
 457                         -- 0x8000 - 0x8FFF: Tumbl BUS
 458
 459                         if address_f_s < "0001000000000000" then                  -- Tumbl
 460                                 tumbl_ce_s             <= '1';
 461                                 data_o_s               <= tumbl_out_s;
 462                         elsif address_f_s(15 downto 2) = "00011111111111" then    -- Measurement
 463                                 meas_ce_s              <= '1';
 464                                 data_o_s               <= meas_out_s;
 465                         elsif address_f_s(15) = '1' then                          -- Tumbl External BUS
 466                                 master_tumbl_xmem_ce_s <= '1';
 467                                 data_o_s               <= master_tumbl_xmem_out_s;
 468                         end if;
 469
 470                 end if;
 471
 472         end process;
 473
 474 -- If RD and BLS is not high, we must keep DATA at high impedance
 475 -- or the FPGA collides with SDRAM (damaging each other)
 476 memory_bus_out:
 477         process(cs0_xc, rd, data_read_s)
 478         begin
 479
 480                 -- CS0 / RD / BLS are active LOW
 481                 if cs0_xc = '0' and rd = '0' then
 482                         -- Don't risk flipping (between data_o_s and latched data_read_s, it's better to wait)
 483                         -- Maybe check this later.
 484                         -- if last_i_rd_s = '1' then
 485                         --   data <= data_o_s;
 486                         -- else
 487                         data <= data_read_s;
 488                         -- end if;
 489                 else
 490                         -- IMPORTANT!!!
 491                         data <= (others => 'Z');
 492                 end if;
 493
 494         end process;
 495
 496 -- Outputs from Tumbl (enabling and address muxing) and Master CPU
 497 tumbl_bus_o:
 498         process(tumbl_xmemb_sel_s, tumbl_xmemb_o_s, master_tumbl_xmem_ce_s, address_f_s, i_rd_s, i_bls_s)
 499                 variable addr_v : std_logic_vector(14 downto 0); -- This space is visible by both (32-bit)
 500                 variable sel_v  : std_logic;
 501         begin
 502
 503                 -- Defaults
 504                 irc_proc_next_ce_s        <= '0';
 505                 lxmaster_next_ce_s        <= '0';
 506                 master_tumbl_xmem_lock_s  <= '0';
 507                 --
 508                 addr_v                    := (others => '0');
 509                 sel_v                     := '0';
 510
 511                 -- Check who is accessing
 512                 if master_tumbl_xmem_ce_s = '1' and (i_rd_s = '1' or i_bls_s /= "0000") then
 513                         -- Master blocks Tumbl
 514                         master_tumbl_xmem_lock_s <= '1';
 515                         addr_v                   := address_f_s(14 downto 0);
 516                         sel_v                    := '1';
 517                 else
 518                         addr_v                   := tumbl_xmemb_o_s.addr;
 519                         sel_v                    := '1';
 520                 end if;
 521
 522                 if sel_v = '1' then
 523                         -- IRC:       0x0800 - 0x081F (32-bit address)
 524                         -- LX MASTER: 0x1000 - 0x17FF (32-bit address)
 525                         if addr_v(14 downto 5) = "0001000000" then
 526                                 irc_proc_next_ce_s     <= '1';
 527                         elsif addr_v(14 downto 11) = "0010" then
 528                                 lxmaster_next_ce_s     <= '1';
 529                         end if;
 530                 end if;
 531
 532         end process;
 533
 534 -- Inputs to Tumbl (enabling and address muxing)
 535 tumbl_bus_i:
 536         process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s, tumbl_xmemb_i_s)
 537         begin
 538
 539                 tumbl_xmemb_i_s.data  <= (others => 'X');
 540
 541                 -- NOTE: This is input to Tumbl EXEQ - with MUL instruction for input > 18-bit,
 542                 -- (i.e. more DSPs in a sequence), this already has tough timing constraints
 543                 -- and SmartXplorer has to be used with XiSE or use Synplify.
 544                 if irc_proc_ce_s = '1' then
 545                         tumbl_xmemb_i_s.data <= irc_proc_out_s;
 546                 elsif lxmaster_ce_s = '1' then
 547                         tumbl_xmemb_i_s.data(15 downto 0)  <= lxmaster_out_s;
 548                         tumbl_xmemb_i_s.data(31 downto 16) <= (others => '0');
 549                 end if;
 550
 551                 master_tumbl_xmem_out_s <= tumbl_xmemb_i_s.data;
 552
 553         end process;
 554
 555 end Behavioral;
 556