hw/bus_lxmaster.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_unsigned.all;
   4 use ieee.numeric_std.all;
   5 use work.lx_rocon_pkg.all;
   6
   7 -- LX Master bus interconnect
   8 entity bus_lxmaster is
   9         port
  10         (
  11                 clk_i        : in std_logic;
  12                 reset_i      : in std_logic;
  13                 -- Data bus
  14                 address_i    : in std_logic_vector(10 downto 0);
  15                 next_ce_i    : in std_logic;
  16                 data_i       : in std_logic_vector(15 downto 0);
  17                 data_o       : out std_logic_vector(15 downto 0);
  18                 --
  19                 bls_i        : in std_logic_vector(1 downto 0);
  20                 --
  21                 rx_done_o    : out std_logic;
  22                 -- Signals for LX Master
  23                 clock_i      : in std_logic;
  24                 miso_i       : in std_logic;
  25                 sync_i       : in std_logic;
  26                 --
  27                 clock_o      : out std_logic;
  28                 mosi_o       : out std_logic;
  29                 sync_o       : out std_logic
  30         );
  31 end bus_lxmaster;
  32
  33 architecture Behavioral of bus_lxmaster is
  34
  35         signal mem_trans_en_s       : std_logic;
  36         signal mem_trans_bls_s      : std_logic_vector(1 downto 0);
  37         signal mem_trans_addr_s     : std_logic_vector(8 downto 0);
  38         signal mem_trans_data_s     : std_logic_vector(15 downto 0);
  39         signal mem_trans_out_s      : std_logic;
  40         signal mem_trans_out_r      : std_logic;
  41         --
  42         signal mem_recv_en_s        : std_logic;
  43         signal mem_recv_bls_s       : std_logic_vector(1 downto 0);
  44         signal mem_recv_addr_s      : std_logic_vector(8 downto 0);
  45         signal mem_recv_data_s      : std_logic_vector(15 downto 0);
  46         signal mem_recv_out_s       : std_logic;
  47         signal mem_recv_out_r       : std_logic;
  48         --
  49         signal state_o_s            : std_logic_vector(1 downto 0);
  50         signal state_o_r            : std_logic_vector(1 downto 0);
  51         --
  52         signal reset_reg_s          : std_logic;
  53         signal reset_reg_r          : std_logic;
  54         signal reset_reg_wr_s       : std_logic;
  55         --
  56         signal reset_s              : std_logic;
  57         signal ce_s                 : std_logic;
  58         --
  59         signal register_trans_in_s  : std_logic;
  60         signal register_trans_out_s : std_logic_vector(1 downto 0);
  61         signal register_trans_wr_s  : std_logic;
  62         signal wdog_trans_in_s      : std_logic;
  63         signal wdog_trans_wr_s      : std_logic;
  64         --
  65         signal register_recv_in_s   : std_logic;
  66         signal register_recv_out_s  : std_logic_vector(1 downto 0);
  67         signal register_recv_wr_s   : std_logic;
  68
  69 begin
  70
  71 master_transmitter: lxmaster_transmitter
  72         port map
  73         (
  74                 clk_i            => clk_i,
  75                 reset_i          => reset_s,
  76                 -- Transmission
  77                 clock_o          => clock_o,
  78                 mosi_o           => mosi_o,
  79                 sync_o           => sync_o,
  80                 -- Register
  81                 register_i       => register_trans_in_s,
  82                 register_o       => register_trans_out_s,
  83                 register_we_i    => register_trans_wr_s,
  84                 -- Watchdog
  85                 wdog_i           => wdog_trans_in_s,
  86                 wdog_we_i        => wdog_trans_wr_s,
  87                 -- BRAM
  88                 mem_clk_i        => clk_i,
  89                 mem_en_i         => mem_trans_en_s,
  90                 mem_we_i         => mem_trans_bls_s,
  91                 mem_addr_i       => mem_trans_addr_s,
  92                 mem_data_i       => data_i,
  93                 mem_data_o       => mem_trans_data_s
  94         );
  95
  96 master_receiver: lxmaster_receiver
  97         port map
  98         (
  99                 clk_i            => clk_i,
 100                 reset_i          => reset_s,
 101                 -- Receiver serial data
 102                 clock_i          => clock_i,
 103                 miso_i           => miso_i,
 104                 sync_i           => sync_i,
 105                 -- Receive done pulse
 106                 rx_done_o        => rx_done_o,
 107                 -- Register
 108                 register_i       => register_recv_in_s,
 109                 register_o       => register_recv_out_s,
 110                 register_we_i    => register_recv_wr_s,
 111                 -- BRAM
 112                 mem_clk_i        => clk_i,
 113                 mem_en_i         => mem_recv_en_s,
 114                 mem_we_i         => mem_recv_bls_s,
 115                 mem_addr_i       => mem_recv_addr_s,
 116                 mem_data_i       => data_i,
 117                 mem_data_o       => mem_recv_data_s
 118         );
 119
 120         reset_s <= reset_reg_r or reset_i;
 121
 122 wire_in:
 123         process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, mem_trans_data_s,
 124                 mem_recv_data_s, data_i, register_trans_out_s, register_recv_out_s)
 125         begin
 126
 127                 mem_trans_en_s       <= '0';
 128                 mem_trans_out_s      <= '0';
 129                 mem_trans_bls_s      <= (others => '0');
 130                 mem_trans_addr_s     <= (others => '0');
 131                 mem_recv_en_s        <= '0';
 132                 mem_recv_out_s       <= '0';
 133                 mem_recv_bls_s       <= (others => '0');
 134                 mem_recv_addr_s      <= (others => '0');
 135                 state_o_s            <= (others => '0');
 136                 reset_reg_s          <= '0';
 137                 reset_reg_wr_s       <= '0';
 138                 register_trans_in_s  <= '0';
 139                 register_trans_wr_s  <= '0';
 140                 register_recv_in_s   <= '0';
 141                 register_recv_wr_s   <= '0';
 142                 wdog_trans_in_s      <= '0';
 143                 wdog_trans_wr_s      <= '0';
 144
 145                 -- Incoming bus request
 146                 if next_ce_i = '1' then
 147
 148                         -- Mapping:
 149                         -- 00 & xxxxxxxx - LX Master transmitter BRAM
 150                         -- 01 & xxxxxxxx - LX Master receiver BRAM
 151                         -- 10 & 00000000 - LX Master reset
 152                         -- 10 & 00000001 - LX Master transmitter register
 153                         -- 10 & 00000010 - LX Master watchdog
 154                         -- 10 & 00000011 - LX Master cycle period register
 155                         -- 10 & 00000100 - LX Master receiver control register
 156                         if address_i(10 downto 9) = "00" then
 157
 158                                 mem_trans_addr_s    <= address_i(8 downto 0);
 159                                 mem_trans_en_s      <= '1';
 160                                 mem_trans_bls_s     <= bls_i;
 161                                 mem_trans_out_s     <= '1';
 162
 163                         elsif address_i(10 downto 9) = "01" then
 164
 165                                 mem_recv_addr_s     <= address_i(8 downto 0);
 166                                 mem_recv_en_s       <= '1';
 167                                 mem_recv_bls_s      <= bls_i;
 168                                 mem_recv_out_s      <= '1';
 169
 170                         else
 171
 172                                 if address_i(8 downto 3) = "000000" then
 173
 174                                         if address_i(2 downto 0) = "000" then
 175                                                 -- LX Master reset
 176                                                 if bls_i(0) = '1' then
 177                                                         reset_reg_s          <= data_i(0);
 178                                                         reset_reg_wr_s       <= '1';
 179                                                 else
 180                                                         -- Ugh, hack :-)
 181                                                         state_o_s(0)         <= reset_reg_r;
 182                                                         state_o_s(1)         <= '0';
 183                                                 end if;
 184                                         elsif address_i(2 downto 0) = "001" then
 185                                                 -- LX Master register
 186                                                 if bls_i(0) = '1' then
 187                                                         register_trans_in_s  <= data_i(0);
 188                                                         register_trans_wr_s  <= '1';
 189                                                 else
 190                                                         state_o_s            <= register_trans_out_s;
 191                                                 end if;
 192                                         elsif address_i(2 downto 0) = "010" then
 193                                                 if bls_i(0) = '1' then
 194                                                         wdog_trans_in_s      <= data_i(0);
 195                                                         wdog_trans_wr_s      <= '1';
 196                                                 end if;
 197                                         elsif address_i(2 downto 0) = "100" then
 198                                                 if bls_i(0) = '1' then
 199                                                         register_recv_in_s  <= data_i(0);
 200                                                         register_recv_wr_s  <= '1';
 201                                                 else
 202                                                         state_o_s            <= register_recv_out_s;
 203                                                 end if;
 204                                         end if;
 205
 206                                 end if;
 207                         end if;
 208                 end if;
 209
 210         end process;
 211
 212 wire_out:
 213         process(ce_s, mem_trans_data_s, mem_trans_out_r,
 214                 mem_recv_data_s, mem_recv_out_r, state_o_r)
 215         begin
 216
 217                 data_o <= (others => '0');
 218
 219                 if ce_s = '1' then
 220                         if mem_trans_out_r = '1' then
 221                                 data_o             <= mem_trans_data_s;
 222                         elsif mem_recv_out_r = '1' then
 223                                 data_o             <= mem_recv_data_s;
 224                         else
 225                                 data_o(1 downto 0) <= state_o_r;
 226                         end if;
 227                 end if;
 228
 229         end process;
 230
 231 update:
 232         process
 233         begin
 234                 wait until clk_i'event and clk_i= '1';
 235                 ce_s            <= next_ce_i;
 236                 mem_trans_out_r <= mem_trans_out_s;
 237                 mem_recv_out_r  <= mem_recv_out_s;
 238                 state_o_r       <= state_o_s;
 239
 240                 if reset_i = '1' then
 241                         reset_reg_r   <= '1';
 242                 elsif reset_reg_wr_s = '1' then
 243                         reset_reg_r   <= reset_reg_s;
 244                 end if;
 245
 246         end process;
 247
 248 end Behavioral;