volatile void *lxpwr_rx_data_hist_buff;
volatile void *lxpwr_rx_data_hist_buff_end;
+uint32_t lxpwr_rx_last_irq;
+uint32_t lxpwr_rx_cycle_time;
+uint32_t lxpwr_rx_irq_latency;
+uint32_t lxpwr_rx_irq_latency_max;
+
IRQ_HANDLER_FNC(lxpwr_rx_done_isr)
{
uint32_t ir;
cr0 = LXPWR_RX_TIM->CR0;
cr1 = LXPWR_RX_TIM->CR1;
+ lxpwr_rx_cycle_time = cr1 - lxpwr_rx_last_irq;
+ lxpwr_rx_last_irq = cr1;
+
hal_gpio_set_value(T2MAT0_PIN, 1);
hal_gpio_set_value(T2MAT1_PIN, 0);
hal_gpio_set_value(T2MAT0_PIN, 0);
}
lxpwr_rx_data_hist_buff = pbuf;
}
+
+ lxpwr_rx_irq_latency = LXPWR_RX_TIM->TC - cr1;
+ if (lxpwr_rx_irq_latency > lxpwr_rx_irq_latency_max)
+ lxpwr_rx_irq_latency_max = lxpwr_rx_irq_latency;
}
return IRQ_HANDLED;
return 0;
}
+int cmd_do_testlxpwrstat(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ printf("lxpwrrx period %ld latency %ld max %ld\n",
+ (long)lxpwr_rx_cycle_time, (long)lxpwr_rx_irq_latency,
+ (long)lxpwr_rx_irq_latency_max);
+ return 0;
+}
+
cmd_des_t const cmd_des_test_memusage = {0, 0,
"memusage", "report memory usage", cmd_do_test_memusage,
{
cmd_do_testlxpwrrx, {(void *)0}
};
+cmd_des_t const cmd_des_testlxpwrstat = {0, 0,
+ "testlxpwrstat", "lxpwr interrupt statistic",
+ cmd_do_testlxpwrstat, {(void *)0}
+ };
+
cmd_des_t const *const cmd_appl_tests[] =
{
&cmd_des_test_memusage,
&cmd_des_testsdram,
#endif /*SDRAM_BASE*/
&cmd_des_testlxpwrrx,
+ &cmd_des_testlxpwrstat,
NULL
};