]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/history - hw/lx_adc_if.vhd
Clean DAD test code a little to use symbolic names for registers and bits.
[fpga/lx-cpu1/lx-dad.git] / hw / lx_adc_if.vhd
2015-05-20 Jan Novotnyfixed FPGA buggs, added support for single shot measure...
2015-04-30 Jan Novotnyadded sensor clock generation files addn ADC readout...