]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/commit
added sensor clock generation files addn ADC readout and control
authorJan Novotny <caca@caca>
Thu, 30 Apr 2015 12:17:53 +0000 (14:17 +0200)
committerJan Novotny <caca@caca>
Thu, 30 Apr 2015 12:17:53 +0000 (14:17 +0200)
commit438161fda132c10604f49c16aa81a0fc27021aeb
treeab3c2f5dd6f6fada8f7407d99b99fd0ff8b9f380
parent09e29375dbdfbd01106739a017f691a8601e271d
added sensor clock generation files addn ADC readout and control
hw/clockgen.vhd [new file with mode: 0644]
hw/lx_adc_if.vhd [new file with mode: 0644]