hw/clockgen.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 use work.lx_dad_pkg.all;
   6
   7 entity clockgen is
   8         port
   9         (
  10                 -- inputs
  11                 clk_i   : in std_logic;
  12                 reset_i : in std_logic;
  13                 sck_i   : in std_logic;
  14                 SDI             : in std_logic;
  15                 -- outputs
  16                 phi_1   : out std_logic;
  17                 phi_2   : out std_logic;
  18                 phi_st  : out std_logic;
  19                 ph_rst  : out std_logic;
  20         --      LED             : out std_logic;
  21                 sck_o   : out std_logic;
  22                 cnv_o   : out std_logic;
  23
  24
  25                 mem_o           : out std_logic_vector(31 downto 0);
  26
  27                 --memory related outputs
  28                 addr_o  : out std_logic_vector(10 downto 0);
  29                 bls_o   : out std_logic_vector(3 downto 0);
  30                 ce_o    : out std_logic;
  31
  32                 -- mem related inputs
  33
  34                 addr_i  : in std_logic_vector(3 downto 0);
  35                 data_i  : in std_logic_vector(31 downto 0);
  36                 ce_i    : in std_logic;
  37                 bls_i   : in std_logic_vector(3 downto 0);
  38                 data_o  : out std_logic_vector(31 downto 0)
  39
  40         );
  41 end clockgen;
  42
  43 architecture rtl of clockgen is
  44
  45         --constant CLK_MASTER_FREQ: unsigned := 50000000;
  46
  47         signal cntra    : unsigned(31 downto 0) := (others => '0');
  48         signal pixel            : integer range 0 to 2047;
  49
  50         signal cntrb    : unsigned(31 downto 0) := (others => '0');
  51
  52         signal bank             : std_logic;
  53
  54         signal run_readout      : std_logic;
  55         signal conv_start       : std_logic;
  56         signal adc_data_i       : std_logic_vector(17 downto 0);
  57         signal adc_drdy_i       : std_logic;
  58         signal run_single       : std_logic;
  59         signal run_single_last : std_logic;
  60         signal run_single_i     : std_logic;
  61         signal finished         : std_logic:='0';
  62         signal finished_i       : std_logic:='0';
  63         signal stability_m      : std_logic;
  64
  65         type    states_i        is (i0, i1, i2, i3, i4, i5, i6, i7, i8, iddle);
  66         signal  state_i         : states_i;
  67
  68         type    meas_states is (normal, multi_per_pixel, leakage);
  69         signal state_meas       : meas_states;
  70
  71         signal  t1              : unsigned(31 downto 0);
  72         signal  t2              : unsigned(31 downto 0);
  73         signal  t3              : unsigned(31 downto 0);
  74         signal  t4              : unsigned(31 downto 0);
  75         signal  t5              : unsigned(31 downto 0);
  76         signal  t6              : unsigned(31 downto 0);
  77         signal  t7              : unsigned(31 downto 0);
  78         signal          t8              : unsigned(31 downto 0);
  79         signal          t9              : unsigned(31 downto 0) ;
  80
  81
  82         signal alive_cntr : integer range 0 to 24999999:=0;
  83         signal LED_latch  : std_logic:='1';
  84
  85 begin
  86
  87         snsor_adc_interface:lx_adc_if
  88         generic map
  89         (
  90                 adc_res         => 18,
  91                 conv_cycles     => 85
  92         )
  93         port map
  94         (
  95                 clk_i           => clk_i,
  96                 rst_i           => reset_i,
  97                 conv_start      => conv_start,
  98                 sck_o           => sck_o,
  99                 cnv_o           => cnv_o,
 100                 data_o          => adc_data_i,
 101                 drdy_o          => adc_drdy_i,
 102                 sck_i           => sck_i,
 103                 SDI                     => sdi
 104         );
 105
 106         -- adc_read : process(reset_i,clk_i)
 107         -- begin
 108                 -- if reset_i = '1' then
 109                 -- elsif rising_edge(clk_i) then
 110                         -- if adc_drdy_i = '1' and pixel < 1025 then
 111                                 --mem_o <= std_logic_vector(resize(unsigned(adc_data_i), mem_o'length));
 112                                 -- mem_o <= std_logic_vector(to_unsigned((pixel),32));
 113                                 -- addr_o <= bank & std_logic_vector(to_unsigned((pixel),10));
 114                                 -- bls_o <= "1111";
 115                                 -- ce_o <= '1';
 116                         -- end if;
 117                 -- end if;
 118         -- end process;
 119
 120         interf : process(reset_i,clk_i)
 121         begin
 122                 if reset_i = '1' then                   -- set default timing
 123                         t1 <= "00000000000000000000000000000110";       --6
 124                         t2 <= "00000000000000000000001111101000";       --9
 125                         t3 <= "00000000000000000000010001111101";       --1149
 126                         t4 <= "00000000000000000000001111101000";       --14
 127                         t5 <= "00000000000000000000000000000110";       --6
 128                         t6 <= "00000000000000000000001001010111";       --599
 129                         t7 <= "00000000000000000000001010010010";       --658
 130                         t8 <= "00000000000000000001001100010000";       --4880
 131                         t9 <= "00000000000000000000000111110011";
 132                         data_o <= (others => '0');
 133                         run_single <= '0';
 134                         run_readout <= '0';
 135                 elsif rising_edge(clk_i) then
 136                         run_single <= '0';
 137                         if finished = '1' then
 138                                 run_readout <= '0';
 139                                 finished_i <= '1';
 140                         end if;
 141                         if ce_i = '1' and bls_i /= "0000" then
 142                                 if addr_i = "0000" then
 143                                         run_readout <= data_i(0);       --start/stop the readout
 144                                         if data_i(1) = '1'  then
 145                                                 run_readout <= '1';
 146                                                 run_single <= '1';
 147                                         end if;
 148                                         if data_i(3) = '1' then
 149                                                 state_meas <= normal;
 150                                         elsif data_i(4) = '1' then
 151                                                 state_meas <= leakage;
 152                                         end if;
 153                                 elsif addr_i = "0001" then
 154                                         t1 <= unsigned(data_i);
 155                                 elsif addr_i = "0010" then
 156                                         t2 <= unsigned(data_i);
 157                                 elsif addr_i = "0011" then
 158                                         t3 <= unsigned(data_i);
 159                                 elsif addr_i = "0100" then
 160                                         t4 <= unsigned(data_i);
 161                                 elsif addr_i = "0101" then
 162                                         t5 <= unsigned(data_i);
 163                                 elsif addr_i = "0110" then
 164                                         t6 <= unsigned(data_i);
 165                                 elsif addr_i <= "0111" then
 166                                         t7 <= unsigned(data_i);
 167                                 elsif addr_i <= "1000" then
 168                                         t8 <= unsigned(data_i);
 169                                 elsif addr_i <= "1001" then
 170                                         t9 <= unsigned(data_i);
 171                                 end if;
 172                         end if;
 173                         if ce_i = '1' then
 174                                 if addr_i = "0000" then
 175                                         data_o <= (others => '0');
 176                                         data_o(2) <= not bank;
 177                                         data_o(6) <= finished_i;
 178                                         data_o(0) <= run_readout;
 179                                         if state_meas = leakage then
 180                                                 data_o(4) <= '1';
 181                                         elsif state_meas = normal then
 182                                                 data_o(3) <= '1';
 183                                         elsif state_meas = multi_per_pixel then
 184                                                 data_o(5) <= '1';
 185                                         end if;
 186                                         finished_i <= '0';
 187                                 elsif addr_i = "0001" then
 188                                         data_o <= std_logic_vector(t1);
 189                                 elsif addr_i = "0010" then
 190                                         data_o <= std_logic_vector(t2);
 191                                 elsif addr_i = "0011" then
 192                                         data_o <= std_logic_vector(t3);
 193                                 elsif addr_i = "0100" then
 194                                         data_o <= std_logic_vector(t4);
 195                                 elsif addr_i = "0101" then
 196                                         data_o <= std_logic_vector(t5);
 197                                 elsif addr_i = "0110" then
 198                                         data_o <= std_logic_vector(t6);
 199                                 elsif addr_i = "0111" then
 200                                         data_o <= std_logic_vector(t7);
 201                                 elsif addr_i = "1000" then
 202                                         data_o <= std_logic_vector(t8);
 203                                 elsif addr_i = "1001" then
 204                                         data_o <= std_logic_vector(t9);
 205                                 end if;
 206                         end if;
 207                 end if;
 208         end process;
 209
 210
 211         proc : process(clk_i, reset_i)
 212         begin
 213                 if reset_i='1' then
 214                         state_i <= i0;
 215                         cntra <= (others => '0');
 216                         pixel <= 0;
 217                         phi_st <= '0';
 218                         bank <= '0';
 219                         ce_o <= '0';
 220                         bls_o <= "0000";
 221                 elsif rising_edge(clk_i) then
 222                         ce_o <= '0';
 223                         bls_o <= "0000";
 224                         conv_start <= '0';
 225                         finished <= '0';
 226                         if run_single = '1' then
 227                                 run_single_i <= '1';
 228                         end if;
 229                         if run_readout = '1' then
 230                                 cntrb <= cntrb + 1;
 231                         else
 232                                 cntrb <= (others => '0');
 233                         end if;
 234                 --      if start_readout = '1' then
 235                 --              pixel <= 0;
 236                 --      end if;
 237                         if cntra = 0 then
 238                                 case state_meas is
 239                                 when leakage =>
 240                                         case state_i is
 241                                         when i0 =>
 242                                                 if pixel > 0 then
 243                                                         mem_o <= "00000000000000"&adc_data_i;
 244                                                         --mem_o <= std_logic_vector(to_unsigned((pixel-1),32));
 245                                                         addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
 246                                                         bls_o <= "1111";
 247                                                         ce_o <= '1';
 248                                                 end if;
 249                                                 if pixel > 1023 then
 250                                                         bank <= not bank;
 251                                                         state_i <= iddle;
 252                                                         if run_single_i = '1' and run_single_last = '0' then
 253                                                                 run_single_last <= '1';
 254                                                         end if;
 255                                                         if run_single_i = '1' and run_single_last = '1' then
 256                                                                 run_single_i <= '0';
 257                                                                 run_single_last <= '0';
 258                                                                 finished <= '1';
 259                                                         end if;
 260                                                 end if;
 261                                                 pixel <= pixel +1;
 262                                                 conv_start <= '1';
 263                                                 cntra <= t9;
 264                                         when others =>
 265                                                 pixel <= 0;
 266                                                 cntra <= (others => '0');
 267                                                 ph_rst <= '0';
 268                                                 if  cntrb > t8 then
 269                                                         state_i <= i0;
 270                                                         cntra <= t9;
 271                                                         cntrb <= (others => '0');
 272                                                         ph_rst <= '1';
 273                                                 end if;
 274                                         end case;
 275                                 when normal =>
 276                                         case state_i is
 277                                         when i0 =>
 278                                                 if pixel > 0 and pixel < 1025 then
 279                                                         mem_o <= "00000000000000"&adc_data_i;
 280                                                         --mem_o <= std_logic_vector(to_unsigned((pixel-1),32));
 281                                                         addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
 282                                                         bls_o <= "1111";
 283                                                         ce_o <= '1';
 284                                                 end if;
 285                                                 state_i <= i1;
 286                                                 cntra<=t1;
 287                                                 phi_2 <= '0';
 288                                         when i1 =>
 289                                                 state_i <= i2;
 290                                                 phi_1 <= '1';
 291                                                 cntra<=t2;
 292                                         when i2 =>
 293                                                 state_i <= i3;
 294                                                 ph_rst <= '0';
 295                                                 cntra<=t3;
 296                                         when i3 =>
 297                                                 ph_rst <= '1';
 298                                                 phi_st <= '0';
 299                                                 state_i <= i4;
 300                                                 cntra<=t4;
 301                                         when i4 =>
 302                                                 phi_1 <= '0';
 303                                                 if pixel = 1026 then
 304                                                         bank <= not bank;
 305                                                         state_i <= iddle;
 306                                                         cntra <= (others => '0');
 307                                                         if run_single_i = '1' and run_single_last = '0' then
 308                                                                 run_single_last <= '1';
 309                                                         end if;
 310                                                         if run_single_i = '1' and run_single_last = '1' then
 311                                                                 run_single_i <= '0';
 312                                                                 run_single_last <= '0';
 313                                                                 finished <= '1';
 314                                                         end if;
 315                                                 else
 316                                                         state_i <= i5;
 317                                                         cntra<=t5;
 318                                                 end if;
 319                                         when i5 =>
 320                                                 phi_2 <= '1';
 321                                                 state_i <= i6;
 322                                                 cntra <= t6;
 323                                         when i6 =>
 324                                                 state_i <= i0;
 325                                                 -- start the readout from adc
 326                                                 cntra <= t7;
 327                                                 if run_readout = '1' then
 328                                                         if pixel > 0 then
 329                                                                 conv_start <= '1';
 330                                                         end if;
 331                                                         if pixel = 0 then
 332                                                                 phi_st <= '1';
 333                                                         end if;
 334                                                 end if;
 335                                                 pixel <= pixel + 1;
 336                                         when others =>
 337                                                 if cntrb > t8 then
 338                                                         cntrb <= (others => '0');
 339                                                         state_i <= i1;
 340                                                 end if;
 341                                                 pixel <= 0;
 342                                                 phi_1 <= '0';
 343                                                 phi_2 <= '0';
 344                                                 ph_rst <= '0';
 345                                                 cntra <= (others => '0');
 346                                         end case;
 347                                 when others =>
 348                                 end case;
 349                         else
 350                                 cntra <= cntra - 1;
 351                         end if;
 352                 end if;
 353         end process;
 354
 355         alive : process(clk_i,reset_i)
 356         begin
 357                 if reset_i = '1' then
 358                         alive_cntr <= 0;
 359                         --LED <= '1';
 360                         LED_latch<= '1';
 361                 elsif rising_edge(clk_i) then
 362                         alive_cntr<=alive_cntr+1;
 363                         if alive_cntr = 24999999 then
 364                                 LED_latch <= not LED_latch;
 365                         --      LED <= LED_latch;
 366                                 alive_cntr<=0;
 367                         end if;
 368                 end if;
 369         end process;
 370 end architecture;