hw/lx_adc_if.vhd

   1 library ieee;\r
   2 use ieee.std_logic_1164.all;\r
   3 use ieee.numeric_std.all;\r
   4 use work.util_pkg.all;\r
   5 use work.lx_dad_pkg.all;\r
   6 \r
   7 entity lx_adc_if is \r
   8 generic\r
   9 (\r
  10         adc_res         : positive := 18;\r
  11         conv_cycles     : integer := 85\r
  12 );\r
  13 port\r
  14 (\r
  15         clk_i   : in std_logic;\r
  16         rst_i   : in std_logic;\r
  17         conv_start      : in std_logic;\r
  18         \r
  19         sck_o   : out std_logic;\r
  20         cnv_o   : out std_logic;\r
  21         data_o  : out std_logic_vector((adc_res-1) downto 0);\r
  22         drdy_o  : out std_logic;\r
  23         \r
  24         sck_i   : in std_logic;\r
  25         SDI             : in std_logic\r
  26 );\r
  27 end lx_adc_if;\r
  28 \r
  29 architecture rtl of lx_adc_if is\r
  30         signal received         : std_logic_vector((adc_res-1) downto 0);\r
  31         signal ckout            : std_logic;\r
  32         --signal active_bit_t   integer range 0 to (adc_res-1);\r
  33         signal active_bit_r     : integer range 0 to (adc_res-1);\r
  34         \r
  35         signal conv_cnter       : integer range 0 to conv_cycles;\r
  36         \r
  37         type    states_i        is (conv, reading, iddle);\r
  38         signal  state_i         : states_i;\r
  39         signal  convert         : std_logic;\r
  40 \r
  41         signal drdy_i           : std_logic;\r
  42         signal drdy_i_last      : std_logic;\r
  43         \r
  44 begin\r
  45 \r
  46         data_sync: process\r
  47         begin\r
  48                 wait until clk_i'event and clk_i = '1';\r
  49                 drdy_i_last <= drdy_i;\r
  50                 drdy_o <= '0';\r
  51                 if drdy_i = '1' and drdy_i_last = '0' then\r
  52                         data_o <= received;\r
  53                         drdy_o <= '1';\r
  54                 end if;\r
  55         end process;\r
  56 \r
  57         adc_readout: process(sck_i, rst_i)\r
  58         begin\r
  59                 if rst_i = '1' then\r
  60                         received <= (others => '0');\r
  61                         active_bit_r <= 17;\r
  62                         drdy_i <= '0';\r
  63                 elsif falling_edge(sck_i) then\r
  64                         if convert = '1' and active_bit_r = 17 then\r
  65                                 received(active_bit_r) <= SDI;\r
  66                                 active_bit_r <= 16;\r
  67                                 drdy_i <= '0';\r
  68                         elsif active_bit_r /= 17 then\r
  69                                 if active_bit_r = 0 then\r
  70                                         drdy_i <= '1';\r
  71                                         active_bit_r <= 17;\r
  72                                 end if;\r
  73                                 received(active_bit_r) <= SDI;\r
  74                         end if;\r
  75                 end if;\r
  76         end process;\r
  77 \r
  78         sck_o <= ckout;\r
  79         adc_control: process(clk_i, rst_i)\r
  80         begin   \r
  81                 if rst_i = '1' then\r
  82                         ckout <= '0';\r
  83                         conv_cnter <= 0;\r
  84                 elsif rising_edge(clk_i) then\r
  85                         case state_i is\r
  86                         when iddle =>\r
  87                                 if conv_start = '1' then\r
  88                                         state_i <= conv;\r
  89                                         cnv_o <= '1';\r
  90                                         convert <= '1';\r
  91                                 end if;\r
  92                         when conv =>\r
  93                                 if conv_cnter = (conv_cycles - 1) then\r
  94                                         conv_cnter <= 0;\r
  95                                         state_i <= reading;\r
  96                                 else\r
  97                                         conv_cnter <= conv_cnter + 1;\r
  98                                 end if;\r
  99                         when reading =>\r
 100                                 if conv_cnter < (adc_res-1) then\r
 101                                         if ckout = '1' then\r
 102                                                 conv_cnter <= conv_cnter + 1;\r
 103                                         end if;\r
 104                                         ckout <= not ckout;\r
 105                                 else\r
 106                                         state_i <= iddle;\r
 107                                         conv_cnter <= 0;\r
 108                                         cnv_o <= '0';\r
 109                                         convert <= '0';\r
 110                                 end if;\r
 111                         end case;\r
 112                 end if;\r
 113         end process;\r
 114 end architecture;\r
 115         \r
 116                 \r
 117                 \r
 118                 \r
 119         \r