extended memotry for 2 samples of sensor data

diff --git a/hw/bus_sensor.vhd b/hw/bus_sensor.vhd
new file mode 100644 (file)
index 0000000..e0c99d8
--- /dev/null
+++ b/hw/bus_sensor.vhd
@@ -0,0 +1,96 @@
+library ieee;\r
+\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+use work.lx_dad_pkg.all;\r
+\r
+-- Connects sampling memory and SPI interface\r
+\r
+entity bus_sensor is\r
+       port\r
+       (\r
+               -- Clock\r
+               clk_i        : in std_logic;\r
+               -- Chip enable\r
+               ce_i         : in std_logic;\r
+               -- Global Reset\r
+               reset_i      : in std_logic;\r
+               -- Master CPU peripheral bus\r
+               bls_i        : in std_logic_vector(3 downto 0);\r
+               address_i    : in std_logic_vector(10 downto 0);\r
+               data_i       : in std_logic_vector(31 downto 0);\r
+               data_o       : out std_logic_vector(31 downto 0);\r
+\r
+               \r
+               -- Memory wiring for internal state automata use\r
+               ce_a_i   : in std_logic;\r
+               adr_a_i  : in std_logic_vector(10 downto 0);\r
+               bls_a_i  : in std_logic_vector(3 downto 0);\r
+               dat_a_i  : in std_logic_vector(31 downto 0)\r
+               -- Non bus signals\r
+               --\r
+               -- Add there external component signals\r
+  );\r
+end bus_sensor;\r
+\r
+architecture Behavioral of bus_sensor is\r
+\r
+       signal sensor_mem_ce_s   : std_logic;\r
+       signal sensor_mem_ce_r   : std_logic;\r
+       signal sensor_mem_bls_s  : std_logic_vector(3 downto 0);\r
+       signal sensor_mem_dout_s : std_logic_vector(31 downto 0);\r
+       \r
+begin\r
+\r
+\r
+\r
+\r
+sensor_mem_instance: sensor_mem\r
+       port map\r
+       (\r
+               -- Memory wiring for internal state automata use\r
+               clk_i  => clk_i,\r
+               ce_i   => ce_a_i,\r
+               adr_i  => adr_a_i,\r
+               bls_i  => bls_a_i,\r
+               dat_i  => dat_a_i,\r
+               dat_o  => open,\r
+               -- Memory wiring for Master CPU\r
+               clk_m  => clk_i,\r
+               en_m   => sensor_mem_ce_s,\r
+               we_m   => sensor_mem_bls_s,\r
+               addr_m => address_i(10 downto 0),\r
+               din_m  => data_i,\r
+               dout_m => sensor_mem_dout_s\r
+       );\r
+\r
+decoder_logic: process(ce_i, address_i, bls_i)\r
+        begin\r
+               sensor_mem_ce_s <= '0';\r
+               sensor_mem_bls_s <= (others => '0');\r
+\r
+               if ce_i = '1' then --and address_i(11 downto 10) = "00" then\r
+                       sensor_mem_ce_s <= '1';\r
+                       sensor_mem_bls_s <= bls_i;\r
+               end if;\r
+       end process;\r
+\r
+output_multiplexer: process(sensor_mem_ce_r, sensor_mem_dout_s)\r
+        begin\r
+               data_o <= (others => '0');\r
+\r
+               if sensor_mem_ce_r = '1' then\r
+                       data_o <= sensor_mem_dout_s;\r
+               end if;\r
+       end process;\r
+\r
+sync_update:\r
+       process\r
+       begin\r
+               wait until clk_i = '1' and clk_i'event;\r
+\r
+               sensor_mem_ce_r <= sensor_mem_ce_s;\r
+       end process;\r
+\r
+\r
+end Behavioral;\r

diff --git a/hw/sensor_mem.vhd b/hw/sensor_mem.vhd
new file mode 100644 (file)
index 0000000..1604929
--- /dev/null
+++ b/hw/sensor_mem.vhd
@@ -0,0 +1,63 @@
+library ieee;\r
+\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+use work.lx_dad_pkg.all;\r
+\r
+-- 8 kB memory for data read from sensor\r
+-- Can be accessed from the Master CPU\r
+\r
+entity sensor_mem is\r
+       port\r
+       (\r
+               -- Memory wiring for internal state automata use\r
+               clk_i  : in std_logic;\r
+               ce_i   : in std_logic;\r
+               adr_i  : in std_logic_vector(10 downto 0);\r
+               bls_i  : in std_logic_vector(3 downto 0);\r
+               dat_i  : in std_logic_vector(31 downto 0);\r
+               dat_o  : out std_logic_vector(31 downto 0);\r
+               -- Memory wiring for Master CPU\r
+               clk_m  : in std_logic;\r
+               en_m   : in std_logic;\r
+               we_m   : in std_logic_vector(3 downto 0);\r
+               addr_m : in std_logic_vector(10 downto 0);\r
+               din_m  : in std_logic_vector(31 downto 0);\r
+               dout_m : out std_logic_vector(31 downto 0)\r
+       );\r
+end sensor_mem;\r
+\r
+architecture rtl of sensor_mem is\r
+begin\r
+\r
+I_RAMB: xilinx_dualport_bram\r
+       generic map\r
+       (\r
+               we_width => 4,\r
+               byte_width => 8,\r
+               address_width => 11,\r
+               port_a_type => READ_FIRST,\r
+               port_b_type => READ_FIRST\r
+       )\r
+       port map\r
+       (\r
+               -- Internal state automata port\r
+               clka => clk_i,\r
+               rsta => '0',\r
+               ena => ce_i,\r
+               wea => bls_i,\r
+               addra => adr_i,\r
+               dina => dat_i,\r
+               douta => dat_o,\r
+\r
+               -- Master CPU port\r
+               clkb => clk_m,\r
+               rstb => '0',\r
+               enb => en_m,\r
+               web => we_m,\r
+               addrb => addr_m,\r
+               dinb => din_m,\r
+               doutb => dout_m\r
+       );\r
+\r
+end rtl;
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