hw/bus_measurement.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6 use work.lx_dad_pkg.all;
   7
   8 -- Memory bus measurement
   9 -- Holds the signal for one clock to simulate longest route
  10
  11 entity bus_measurement is
  12         port
  13         (
  14                 -- Clock
  15                 clk_i     : in std_logic;
  16                 -- Reset
  17                 reset_i   : in std_logic;
  18                 -- Chip enable
  19                 ce_i      : in std_logic;
  20                 -- Address
  21                 address_i : in std_logic_vector(1 downto 0);
  22                 -- Data bus
  23                 data_i    : in std_logic_vector(31 downto 0);
  24                 data_o    : out std_logic_vector(31 downto 0);
  25                 -- Bus signals
  26                 bls_i     : in std_logic_vector(3 downto 0)
  27         );
  28 end bus_measurement;
  29
  30 architecture Behavioral of bus_measurement is
  31
  32         -- Wiring
  33         signal meas1_out_s    : std_logic_vector(31 downto 0);
  34         signal meas1_ce_s     : std_logic;
  35         --
  36         signal meas2_out_s    : std_logic_vector(31 downto 0);
  37         signal meas2_ce_s     : std_logic;
  38
  39 begin
  40
  41         -- First measurement register (0xAAAAAAAA)
  42 measurement1: measurement_register
  43         generic map
  44         (
  45                 id_g   => "10101010101010101010101010101010"
  46         )
  47         port map
  48         (
  49                 clk_i    => clk_i,
  50                 ce_i     => meas1_ce_s,
  51                 switch_i => address_i(0),
  52                 reset_i  => reset_i,
  53                 bls_i    => bls_i,
  54                 data_i   => data_i,
  55                 data_o   => meas1_out_s
  56         );
  57
  58         -- Second measurement register (=0x55555555)
  59 measurement2: measurement_register
  60         generic map
  61         (
  62                 id_g   => "01010101010101010101010101010101"
  63         )
  64         port map
  65         (
  66                 clk_i    => clk_i,
  67                 ce_i     => meas2_ce_s,
  68                 switch_i => address_i(0),
  69                 reset_i  => reset_i,
  70                 bls_i    => bls_i,
  71                 data_i   => data_i,
  72                 data_o   => meas2_out_s
  73         );
  74
  75 -- Bus process
  76 update:
  77         process (ce_i, address_i, meas1_out_s, meas2_out_s)
  78         begin
  79
  80                 -- Defaults
  81                 meas1_ce_s <= '0';
  82                 meas2_ce_s <= '0';
  83                 data_o     <= (others => 'X');
  84
  85                 -- Chip Enable
  86                 if ce_i = '1' then
  87                         if address_i(1) = '0' then
  88                                 meas1_ce_s  <= '1';
  89                                 data_o      <= meas1_out_s;
  90                         else
  91                                 meas2_ce_s  <= '1';
  92                                 data_o      <= meas2_out_s;
  93                         end if;
  94                 end if;
  95
  96         end process;
  97
  98 end Behavioral;
  99