Remove nonstandard ieee.std_logic_arith and ieee.std_logic_unsigned libraries.

[fpga/lx-cpu1/lx-dad.git] / hw / lx_dad_pkg.vhd

diff --git a/hw/lx_dad_pkg.vhd b/hw/lx_dad_pkg.vhd
index de69d2c6c5aa30a40d120e250539732a4666779a..02306e20b7ac6701cb8d25c434b254d4414409a8 100644 (file)
--- a/hw/lx_dad_pkg.vhd
+++ b/hw/lx_dad_pkg.vhd
@@ -1,7 +1,5 @@
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 use work.util_pkg.all;
 
@@ -115,6 +113,27 @@ package lx_dad_pkg is
        );
        end component;
 
+       -- Dualported memory for example componenet
+       component lx_example_mem
+       port
+       (
+               -- Memory wiring for internal state automata use
+               clk_i  : in std_logic;
+               ce_i   : in std_logic;
+               adr_i  : in std_logic_vector(9 downto 0);
+               bls_i  : in std_logic_vector(3 downto 0);
+               dat_i  : in std_logic_vector(31 downto 0);
+               dat_o  : out std_logic_vector(31 downto 0);
+               -- Memory wiring for Master CPU
+               clk_m  : in std_logic;
+               en_m   : in std_logic;
+               we_m   : in std_logic_vector(3 downto 0);
+               addr_m : in std_logic_vector(9 downto 0);
+               din_m  : in std_logic_vector(31 downto 0);
+               dout_m : out std_logic_vector(31 downto 0)
+       );
+       end component;
+
        -- Measurement interconnect
        component bus_measurement
        port