hw/clockgen.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 use work.lx_dad_pkg.all;
   6
   7 entity clockgen is
   8         port
   9         (
  10                 -- inputs
  11                 clk_i   : in std_logic;
  12                 reset_i : in std_logic;
  13                 sck_i   : in std_logic;
  14                 SDI             : in std_logic;
  15                 -- outputs
  16                 phi_1   : out std_logic;
  17                 phi_2   : out std_logic;
  18                 phi_st  : out std_logic;
  19                 ph_rst  : out std_logic;
  20                 LED             : out std_logic;
  21                 sck_o   : out std_logic;
  22                 cnv_o   : out std_logic;
  23
  24
  25                 mem_o           : out std_logic_vector(31 downto 0);
  26
  27                 --memory related outputs
  28                 addr_o  : out std_logic_vector(10 downto 0);
  29                 bls_o   : out std_logic_vector(3 downto 0);
  30                 ce_o    : out std_logic;
  31
  32                 -- mem related inputs
  33
  34                 addr_i  : in std_logic_vector(1 downto 0);
  35                 data_i  : in std_logic_vector(31 downto 0);
  36                 ce_i    : in std_logic;
  37                 bls_i   : in std_logic_vector(3 downto 0);
  38                 data_o  : out std_logic_vector(31 downto 0)
  39
  40         );
  41 end clockgen;
  42
  43 architecture rtl of clockgen is
  44
  45         --constant CLK_MASTER_FREQ: unsigned := 50000000;
  46
  47         signal cntra    : unsigned(15 downto 0) := (others => '0');
  48         signal pixel    : integer range 0 to 1024;
  49
  50         signal bank             : std_logic;
  51
  52         signal run_readout      : std_logic;
  53         signal conv_start       : std_logic;
  54         signal adc_data_i       : std_logic_vector(17 downto 0);
  55         signal adc_drdy_i       : std_logic;
  56
  57         type    states_i        is (i0, i1, i2, i3, i4, i5, i6, i7, i8);
  58         signal  state_i         : states_i;
  59
  60         signal  t1              : unsigned(15 downto 0);
  61         signal  t2              : unsigned(15 downto 0);
  62         signal  t3              : unsigned(15 downto 0);
  63         signal  t4              : unsigned(15 downto 0);
  64         signal  t5              : unsigned(15 downto 0);
  65         signal  t6              : unsigned(15 downto 0);
  66         signal  t7              : unsigned(15 downto 0);
  67
  68         signal  t1_i            : std_logic_vector(15 downto 0);
  69         signal  t2_i            : std_logic_vector(15 downto 0);
  70         signal  t3_i            : std_logic_vector(15 downto 0);
  71         signal  t4_i            : std_logic_vector(15 downto 0);
  72         signal  t5_i            : std_logic_vector(15 downto 0);
  73         signal  t6_i            : std_logic_vector(15 downto 0);
  74         signal  t7_i            : std_logic_vector(15 downto 0);
  75
  76
  77         signal alive_cntr : integer range 0 to 24999999:=0;
  78         signal LED_latch  : std_logic:='1';
  79
  80 begin
  81
  82         snsor_adc_interface:lx_adc_if
  83         generic map
  84         (
  85                 adc_res         => 18,
  86                 conv_cycles     => 85
  87         )
  88         port map
  89         (
  90                 clk_i           => clk_i,
  91                 rst_i           => reset_i,
  92                 conv_start      => conv_start,
  93                 sck_o           => sck_o,
  94                 cnv_o           => cnv_o,
  95                 data_o          => adc_data_i,
  96                 drdy_o          => adc_drdy_i,
  97                 sck_i           => sck_i,
  98                 SDI                     => sdi
  99         );
 100
 101         adc_read : process
 102         begin
 103                 wait until clk_i'event and clk_i = '1';
 104                 if reset_i = '1' then
 105                         bank <= '0';
 106                 end if;
 107                 ce_o <= '0';
 108                 bls_o <= "0000";
 109                 if adc_drdy_i = '1' then
 110                         mem_o <= std_logic_vector(resize(unsigned(adc_data_i), mem_o'length));
 111                         addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
 112                         bls_o <= "1111";
 113                         ce_o <= '1';
 114                         if pixel = 1024 then
 115                                 bank <= not bank;
 116                         end if;
 117                 end if;
 118         end process;
 119
 120         interf : process
 121         begin
 122                 wait until clk_i'event and clk_i = '1';
 123                 if reset_i = '1' then                   -- set default timing
 124                         t1 <= "0000000000000010";       --2
 125                         t2 <= "0000000000001001";       --9
 126                         t3 <= "0000010001111101";       --1149
 127                         t4 <= "0000000000001110";       --14
 128                         t5 <= "0000000000000010";       --2
 129                         t6 <= "0000001001010111";       --599
 130                         t7 <= "0000001010010010";       --658
 131                         t1_i <= "0000000000000010";     --2
 132                         t2_i <= "0000000000001001";     --9
 133                         t3_i <= "0000010001111101";     --1149
 134                         t4_i <= "0000000000001110";     --14
 135                         t5_i <= "0000000000000010";     --2
 136                         t6_i <= "0000001001010111";     --599
 137                         t7_i <= "0000001010010010";     --658
 138                         data_o <= (others => '0');
 139                         run_readout <= '0';
 140                 elsif ce_i = '1' and bls_i /= "0000" then
 141                         if addr_i = "00" then
 142                                 t1_i <= data_i(15 downto 0);
 143                                 t2_i <= data_i(31 downto 16);
 144                         elsif addr_i = "01" then
 145                                 t3_i <= data_i(15 downto 0);
 146                                 t4_i <= data_i(31 downto 16);
 147                         elsif addr_i = "10" then
 148                                 t5_i <= data_i(15 downto 0);
 149                                 t6_i <= data_i(31 downto 16);
 150                         elsif addr_i = "11" then
 151                                 run_readout <= data_i(30);      --start/stop the readout
 152                                 if data_i(31) = '1' then        --update timing constnts
 153                                         t1 <= unsigned(t1_i);
 154                                         t2 <= unsigned(t2_i);
 155                                         t3 <= unsigned(t3_i);
 156                                         t4 <= unsigned(t4_i);
 157                                         t5 <= unsigned(t5_i);
 158                                         t6 <= unsigned(t6_i);
 159                                         t7 <= unsigned(t7_i);
 160                                 else
 161                                         t7_i <= data_i(15 downto 0);
 162                                 end if;
 163                         end if;
 164                 end if;
 165                 if addr_i = "11" then
 166                         data_o <= (others => '0');
 167                         data_o(0) <= not bank;
 168                 end if;
 169         end process;
 170
 171
 172         proc : process(clk_i, reset_i)
 173         begin
 174                 if reset_i='1' then
 175                         state_i <= i0;
 176                         cntra <= (others => '0');
 177                         pixel <= 0;
 178                         phi_st <= '0';
 179                 elsif rising_edge(clk_i) then
 180                         conv_start <= '0';
 181                 --      if start_readout = '1' then
 182                 --              pixel <= 0;
 183                 --      end if;
 184                         if cntra = 0 then
 185                                 case state_i is
 186                                 when i0 =>
 187                                         state_i <= i1;
 188                                         cntra<=t1;
 189                                         phi_2 <= '0';
 190                                 when i1 =>
 191                                         state_i <= i2;
 192                                         phi_1 <= '1';
 193                                         cntra<=t2;
 194                                 when i2 =>
 195                                         state_i <= i3;
 196                                         ph_rst <= '1';
 197                                         cntra<=t3;
 198                                 when i3 =>
 199                                         ph_rst <= '0';
 200                                         phi_st <= '0';
 201                                         state_i <= i4;
 202                                         cntra<=t4;
 203                                 when i4 =>
 204                                         phi_1 <= '0';
 205                                         state_i <= i5;
 206                                         cntra<=t5;
 207                                 when i5 =>
 208                                         phi_2 <= '1';
 209                                         state_i <= i6;
 210                                         cntra <= t6;
 211                                 when i6 =>
 212                                         state_i <= i0;
 213                                         conv_start <= '1';
 214                                         -- start the readout from adc
 215                                         cntra <= t7;
 216                                         if run_readout = '1' and pixel = 0 then
 217                                                 phi_st <= '1';
 218                                         end if;
 219                                         if pixel = 1024 then
 220                                                 pixel <= 0;
 221                                         else
 222                                                 pixel <= pixel + 1;
 223                                         end if;
 224                                 when others =>
 225                                         --set 0 to phi1
 226                                         phi_1 <= '1';
 227                                         phi_2 <= '0';
 228                                         state_i <= i0;
 229                                         cntra <= (others => '0');
 230                                 end case;
 231                                 --else
 232                                 --      cntrb <= cntrb + 1;
 233                                 --end if;
 234                         else
 235                                 cntra <= cntra - 1;
 236                         end if;
 237                 end if;
 238         end process;
 239
 240         alive : process(clk_i,reset_i)
 241         begin
 242                 if reset_i = '1' then
 243                         alive_cntr <= 0;
 244                         LED <= '1';
 245                         LED_latch<= '1';
 246                 elsif rising_edge(clk_i) then
 247                         alive_cntr<=alive_cntr+1;
 248                         if alive_cntr = 24999999 then
 249                                 LED_latch <= not LED_latch;
 250                                 LED <= LED_latch;
 251                                 alive_cntr<=0;
 252                         end if;
 253                 end if;
 254         end process;
 255 end architecture;