The first phase of integration of Hynix HMS30c7202 C_CAN support
[lincan.git] / lincan / src / c_can.c
1 /* c_can.c - Hynix HMS30c7202 ARM generic C_CAN module handling
2  * Linux CAN-bus device driver.
3  * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de
4  * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl
5  * and Ake Hedman, eurosource, akhe@eurosource.se
6  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
7  * email:pisa@cmp.felk.cvut.cz
8  * This software is released under the GPL-License.
9  * Version lincan-0.2  9 Jul 2003
10  */
11
12 #define __NO_VERSION__
13
14 #include "../include/can.h"
15 #include "../include/can_sysdep.h"
16 #include "../include/main.h"
17 #include "../include/c_can.h"
18
19 extern int stdmask;
20 extern int extmask;
21
22 can_spinlock_t c_can_spwlock=SPIN_LOCK_UNLOCKED; // Spin lock for write operations
23 can_spinlock_t c_can_sprlock=SPIN_LOCK_UNLOCKED; // Spin lock for read operations
24 can_spinlock_t c_can_if1lock=SPIN_LOCK_UNLOCKED; // spin lock for the if1 register
25 can_spinlock_t c_can_if2lock=SPIN_LOCK_UNLOCKED; // spin lcok for the if2 register
26
27 /**
28  * c_can_enable_configuration - enable chip configuration mode
29  * @pchip: pointer to chip state structure
30  */
31 int c_can_enable_configuration(struct chip_t *pchip)
32 {
33    int i=0;
34    u16 flags;
35    DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n", pchip->chip_nr);
36 /*
37    DEBUGMSG("Trying disable_irq(...) : ");
38    //disable IRQ
39         disable_irq(chip->chip_irq);
40 */
41    //read Control Register
42    flags=c_can_read_reg_w(pchip, CCCR);
43    //set Init-Bit in the Control Register (10 tries)
44    while ((!(flags & CR_INIT)) && (i<=10))
45      {
46         c_can_write_reg_w(pchip,flags|CR_INIT, CCCR);
47         udelay(1000);
48         i++;
49         flags=c_can_read_reg_w(pchip, CCCR);
50      }
51    if (i>=10)
52      {
53         CANMSG("Reset error\n");
54         //enable_irq(chip->chip_irq);
55         return -ENODEV;
56      }
57
58    DEBUGMSG("-> ok\n");
59    return 0;
60 }
61
62 ///////////////////////////////////////////////////////////////////////
63 int c_can_disable_configuration(struct chip_t *pchip)
64 {
65    int i=0;
66    u16 flags;
67
68    DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n", pchip->chip_nr);
69    //read Control Register
70    flags=c_can_read_reg_w(pchip, CCCR);
71
72    //reset Init-Bit in the Control Register (10 tries)
73    while ( (flags & CR_INIT) && (i<=10) )
74      {
75         c_can_write_reg_w( pchip,flags & ~CR_INIT, CCCR);
76         udelay(1000); //100 microseconds
77         i++;
78         flags=c_can_read_reg_w(pchip, CCCR);
79      }
80    if (i>=10)
81      {
82         CANMSG("Error leaving reset status\n");
83         return -ENODEV;
84      }
85
86    //enable IRQ
87    //enable_irq(chip->chip_irq);
88    DEBUGMSG("-> ok\n");
89    return 0;
90 }
91
92 ///////////////////////////////////////////////////////////////////////
93 int c_can_chip_config(struct chip_t *pchip)
94 {
95
96    DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_nr);
97    // Validate pointer
98    if ( NULL == pchip ) return -1;
99
100    if (pchip->baudrate == 0)
101      pchip->baudrate=1000;
102
103    if (c_can_baud_rate(pchip,pchip->baudrate*1000,pchip->clock,0,75,0))
104      {
105         CANMSG("Error configuring baud rate\n");
106         return -ENODEV;
107      }
108         /*if (extended){
109            if (c_can_extended_mask(pchip,0x0000000,extmask)) {
110                    CANMSG("Error configuring extended mask\n");
111                    return -ENODEV;
112       }
113    }else{
114       if (c_can_standard_mask(pchip,0x0000,stdmask)) {
115                    CANMSG("Error configuring standard mask\n");
116                    return -ENODEV;
117            }
118         }*/
119    if (c_can_clear_objects(pchip))
120      {
121         CANMSG("Error clearing message objects\n");
122         return -ENODEV;
123      }
124    if (c_can_config_irqs(pchip, CR_MIE | CR_SIE | CR_EIE))
125      {
126         CANMSG("Error configuring interrupts\n");
127         return -ENODEV;
128      }
129
130    DEBUGMSG("-> Configured successfully\n");
131
132 #ifdef REGDUMP
133    c_can_registerdump(pchip);
134 #endif
135
136    return 0;
137 }
138
139 ///////////////////////////////////////////////////////////////////////
140 /*
141  * Checks if the Busy-Bit in the IF1-Command-Request Register is set
142  */
143 int c_can_if1_busycheck(struct chip_t *pchip)
144 {
145
146    int i=0;
147    unsigned short comreg = 0;
148
149    comreg = c_can_read_reg_w( pchip, CCIF1CR);
150    while ( (comreg & IFXCR_BUSY) && (i<=10) )
151      {
152         udelay(100); //100 microseconds
153         i++;
154         comreg=c_can_read_reg_w( pchip, CCIF1CR);
155      }
156    if (i>=10)
157      {
158         CANMSG("Error Busy-Bit stays set\n");
159         return -ENODEV;
160      }
161
162    return 0;
163 }
164
165 ///////////////////////////////////////////////////////////////////////
166 /*
167  * Checks if the Busy-Bit in the IF2-Command-Request Register is set
168  */
169 int c_can_if2_busycheck(struct chip_t *pchip)
170 {
171
172    int i=0;
173    unsigned short comreg = 0;
174
175    comreg = c_can_read_reg_w( pchip, CCIF2CR);
176    while ( (comreg & IFXCR_BUSY) && (i<=10) )
177      {
178         udelay(100); //100 microseconds
179         i++;
180         comreg=c_can_read_reg_w( pchip, CCIF2CR);
181      }
182    if (i>=10)
183      {
184         CANMSG("Error Busy-Bit stays set\n");
185         return -ENODEV;
186      }
187
188    return 0;
189 }
190
191 ///////////////////////////////////////////////////////////////////////
192 /*
193  * Though the C-CAN Chip can handle one mask for each Message Object, this Method defines
194  * one mask for all MOs. That means every MO gets the same mask.
195  */
196
197 /* Set communication parameters.
198  * param rate baud rate in Hz
199  * param clock frequency of C-CAN clock in Hz
200  * param sjw synchronization jump width (0-3) prescaled clock cycles
201  * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
202  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
203  */
204 int c_can_baud_rate(struct chip_t *pchip, int rate, int clock,
205                         int sjw, int sampl_pt, int flags)
206 {
207    int best_error = 1000000000, error;
208    int best_tseg=0, best_brp=0, best_rate=0, brp=0;
209    int tseg=0, tseg1=0, tseg2=0;
210
211    unsigned short tempCR = 0;
212
213    DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_nr);
214
215    if (c_can_enable_configuration(pchip))
216      return -ENODEV;
217
218    clock /=2;
219
220         /* tseg even = round down, odd = round up */
221    for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++)
222      {
223         brp = clock/((1+tseg/2)*rate)+tseg%2;
224         if (brp == 0 || brp > 64)
225           continue;
226         error = rate - clock/(brp*(1+tseg/2));
227         if (error < 0)
228           error = -error;
229         if (error <= best_error)
230           {
231              best_error = error;
232              best_tseg = tseg/2;
233              best_brp = brp-1;
234              best_rate = clock/(brp*(1+tseg/2));
235           }
236      }
237    if (best_error && (rate/best_error < 10))
238      {
239         CANMSG("baud rate %d is not possible with %d Hz clock\n",
240                rate, 2*clock);
241         CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
242                best_rate, best_brp, best_tseg, tseg1, tseg2);
243         return -EINVAL;
244      }
245    tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
246    if (tseg2 < 0)
247      tseg2 = 0;
248    if (tseg2 > MAX_TSEG2)
249      tseg2 = MAX_TSEG2;
250    tseg1 = best_tseg-tseg2-2;
251    if (tseg1 > MAX_TSEG1)
252      {
253         tseg1 = MAX_TSEG1;
254         tseg2 = best_tseg-tseg1-2;
255      }
256
257    DEBUGMSG("-> Setting %d bps.\n", best_rate);
258    DEBUGMSG("->brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
259             best_brp, best_tseg, tseg1, tseg2,
260             (100*(best_tseg-tseg2)/(best_tseg+1)));
261
262    //read Control Register
263    tempCR = c_can_read_reg_w( pchip, CCCR);
264    //Configuration Change Enable
265    c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
266    c_can_write_reg_w(pchip, ((unsigned short)tseg2)<<12 | ((unsigned short)tseg1)<<8
267                          | (unsigned short)sjw<<6 | (unsigned short) best_brp,
268                          CCBT);
269
270    if (c_can_disable_configuration(pchip))
271      return -ENODEV;
272
273    return 0;
274 }
275
276 ///////////////////////////////////////////////////////////////////////
277 int c_can_mask(struct msgobj_t *pmsgobj,
278                u32 mask,
279                u16 usedirbit)
280 {
281    unsigned short tempreg = 0;
282    unsigned short readMaskCM;
283    unsigned short writeMaskCM;
284
285    DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
286
287    readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK;
288    writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK | IFXCM_WRRD;
289
290    spin_lock( &c_can_if1lock );
291
292    //load Message Object in IF1
293    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
294    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
295    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
296
297    //setting Message Valid Bit to zero
298    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
299    tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
300    c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~(IFXARB2_MVAL), CCIF1A2);
301    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
302    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
303
304    //setting UMask, MsgVal and Mask Register
305    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
306
307    //writing acceptance mask for extended or standart mode
308    if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
309      {
310         if (usedirbit)
311           c_can_write_reg_w(pmsgobj->hostchip, 
312                             (mask>>16 & 0x1FFF) | IFXMSK2_MXTD | IFXMSK2_MDIR, CCIF1M2);
313         else
314           c_can_write_reg_w(pmsgobj->hostchip, 
315                             (mask>>16 & 0x1FFF) | IFXMSK2_MXTD, CCIF1M2);
316         c_can_write_reg_w(pmsgobj->hostchip, (mask & 0xFFFF), CCIF1M1);
317      }
318    else
319      {
320         if (usedirbit)
321           c_can_write_reg_w(pmsgobj->hostchip, 
322                             ((mask<<2) & 0x1FFC) | IFXMSK2_MDIR, CCIF1M2);
323         else
324           c_can_write_reg_w(pmsgobj->hostchip,
325                             ((mask<<2) & 0x1FFC), CCIF1M2);
326         c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
327      }
328    //seting Message Valid Bit to one
329    tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
330    c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
331    //write to chip
332    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
333    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
334
335    spin_unlock( &c_can_if1lock );
336
337    DEBUGMSG("-> Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
338
339 #ifdef REGDUMP
340    c_can_registerdump(pmsgobj->hostchip);
341 #endif
342
343    return 0;
344 }
345
346 ///////////////////////////////////////////////////////////////////////
347 int c_can_use_mask(struct msgobj_t *pmsgobj,
348                    u16 useflag)
349 {
350    unsigned short tempreg = 0;
351    unsigned short readMaskCM;
352    unsigned short writeMaskCM;
353
354 #ifdef DEBUG
355    char *boolstring = "false";
356    if (useflag) boolstring = "true";
357 #endif
358    DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
359
360    readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
361    writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;
362
363    spin_lock( &c_can_if1lock );
364
365    //load Message Object in IF1
366    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
367    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
368    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
369
370    //setting Message Valid Bit to zero
371    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
372    tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
373    c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
374    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
375    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
376
377    //setting UMask bit
378    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
379    if ( useflag )
380      {
381         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
382         c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK, CCIF1DMC);
383      }
384    else
385      {
386         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
387         c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXMC_UMASK, CCIF1DMC);
388      }
389    //seting Message Valid Bit to one
390    tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
391    c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
392    //write to chip
393    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
394    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
395
396    spin_unlock( &c_can_if1lock );
397
398 #ifdef DEBUG
399    DEBUGMSG("-> Setting umask bit to %s\n",boolstring);
400 #endif
401 #ifdef REGDUMP
402    c_can_registerdump(pmsgobj->hostchip);
403 #endif
404
405    return 0;
406 }
407
408 ///////////////////////////////////////////////////////////////////////
409 int c_can_clear_objects(struct chip_t *pchip)
410 {
411    unsigned short i = 0;
412    unsigned short tempreg = 0;
413
414    unsigned short maskCM = IFXCM_ARB;
415
416    DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_nr);
417
418    spin_lock( &c_can_if1lock );
419    spin_lock( &c_can_if2lock );
420
421    for (i=0; i<0x10; i++)
422      {
423
424         //loading Message Objects in IF1 and IF2
425         if (c_can_if1_busycheck(pchip)) return -ENODEV;
426         c_can_write_reg_w(pchip, maskCM, CCIF1CM);
427         c_can_write_reg_w(pchip, i, CCIF1CR);
428         if (c_can_if2_busycheck(pchip)) return -ENODEV;
429         c_can_write_reg_w(pchip, maskCM, CCIF2CM);
430         c_can_write_reg_w(pchip, i+0x10, CCIF2CR);
431
432         //setting Message Valid Bit to zero
433         if (c_can_if1_busycheck(pchip)) return -ENODEV;
434         tempreg = c_can_read_reg_w(pchip, CCIF1A2);
435         c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
436         c_can_write_reg_w(pchip, i, CCIF1CR);
437         if (c_can_if2_busycheck(pchip)) return -ENODEV;
438         tempreg = c_can_read_reg_w(pchip, CCIF2A2);
439         c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF2A2);
440         c_can_write_reg_w(pchip, i+0x10, CCIF2CR);
441      }
442
443    for (i=0; i<pchip->max_objects; i++)
444      {
445         if (can_msgobj_test_fl(pchip->msgobj[i],OPENED))
446           {
447              // In- and output buffer re-initialization
448              canqueue_ends_flush_inlist(pchip->msgobj[i]->qends);
449              canqueue_ends_flush_outlist(pchip->msgobj[i]->qends);
450
451           }
452      }
453
454    spin_unlock( &c_can_if1lock );
455    spin_unlock( &c_can_if2lock );
456
457    DEBUGMSG("-> Message Objects reset\n");
458
459    return 0;
460 }
461
462 ///////////////////////////////////////////////////////////////////////
463 int c_can_config_irqs(struct chip_t *pchip,
464                       u16 irqs)
465 {
466    u16 tempreg;
467
468    DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_nr);
469
470    /*
471     CANMSG("c_can_config_irqs not implemented\n");
472     return -ENOSYS;
473     */
474
475    tempreg = c_can_read_reg_w(pchip, CCCR);
476    //DEBUGMSG("-> CAN Control Register: 0x%.4lx\n",(long)tempreg);
477    c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
478    DEBUGMSG("-> Configured hardware interrupt delivery\n");
479    return 0;
480 }
481
482 ///////////////////////////////////////////////////////////////////////
483 int c_can_pre_read_config(struct chip_t *pchip, struct msgobj_t *pmsgobj)
484 {
485    unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
486    unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
487    unsigned short mcreg = 0;
488    u32 id=pmsgobj->rx_preconfig_id;
489
490    DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
491
492    spin_lock( &c_can_if1lock );
493
494
495    //loading Message Object in IF1
496    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
497    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
498    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
499    //setting Message Valid Bit to zero
500    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
501    c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A2);
502    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
503    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
504    //Configuring Message-Object
505    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
506    mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1CM);
507    c_can_write_reg_w(pmsgobj->hostchip, 
508                      ((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE), CCIF1DMC);
509    //writing arbitration mask for extended or standart mode
510    if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
511      {
512         c_can_write_reg_w(pmsgobj->hostchip, 
513                           IFXARB2_XTD | IFXARB2_MVAL | (id>>16 & 0x1FFF), CCIF1A2);
514         c_can_write_reg_w(pmsgobj->hostchip, id & 0xFFFF, CCIF1A1);
515      }
516    else
517      {
518         c_can_write_reg_w(pmsgobj->hostchip, 
519                           IFXARB2_MVAL | (id<<2 & 0x1FFC), CCIF1A2);
520         //c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
521      }
522    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
523    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
524
525    spin_unlock( &c_can_if1lock );
526
527    DEBUGMSG("-> Receiving through message object %d with id=%d\n", pmsgobj->object,
528             id);
529 #ifdef REGDUMP
530    c_can_registerdump(pmsgobj->hostchip);
531 #endif
532
533    return 0;
534 }
535
536 ///////////////////////////////////////////////////////////////////////
537 int c_can_pre_write_config(struct chip_t *chip, struct msgobj_t *obj, 
538                                 struct canmsg_t *msg)
539 {
540         return 0; 
541 }
542
543  ///////////////////////////////////////////////////////////////////////
544 /*
545  *Prepare the Chip to send specified Message over specified Messageobject
546  *In this version the method also sends the message.
547  */
548
549 int c_can_send_msg(struct chip_t *pchip, struct msgobj_t *pmsgobj,
550                         struct canmsg_t *pmsg)
551 {   
552    unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB;
553    unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD;
554    unsigned short writeSendMskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD | IFXCM_TRND;
555    unsigned short mcreg = 0;
556    //unsigned short arbreg = 0;
557    unsigned short dataA1 = 0;
558    unsigned short dataA2 = 0;
559    unsigned short dataB1 = 0;
560    unsigned short dataB2 = 0;
561
562    DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
563
564    spin_lock( &c_can_if2lock );
565
566    can_msgobj_clear_fl(pmsgobj,RX_MODE);
567    
568    //loading Message Object in IF1
569    if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
570    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF2CM);
571    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
572    //setting Message Valid Bit to zero
573    if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
574    c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF2A2);
575    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF2CM);
576    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
577    //Configuring MO
578    if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
579    mcreg = c_can_read_reg_w( pmsgobj->hostchip, CCIF2CM);
580    //remote enable?
581    //define Command Mask
582    c_can_write_reg_w(pmsgobj->hostchip, (mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_TXIE
583                      | IFXMC_RMTEN | IFXMC_NEWDAT | IFXMC_TXRQST | (pmsg->length & 0xF), CCIF2DMC);
584    //set Arbitration Bits
585    if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
586      {
587         c_can_write_reg_w(pmsgobj->hostchip, (u16)(pmsg->id), CCIF2A1);
588         c_can_write_reg_w(pmsgobj->hostchip, IFXARB2_XTD | IFXARB2_MVAL | IFXARB2_DIR
589                                             | ((u16)(pmsg->id>>16) & 0x1FFF), CCIF2A2);
590      }
591    else
592      {
593         c_can_write_reg_w(pmsgobj->hostchip, 
594                           (IFXARB2_MVAL | IFXARB2_DIR | ((u16)(pmsg->id<<2) & 0x1FFC)), CCIF2A2);
595         c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
596      }
597    //write Data
598    if (pmsg->length>0)
599      {
600         dataA1 = pmsg->data[0] | (u16)pmsg->data[1]<<8;
601         dataA2 = pmsg->data[2] | (u16)pmsg->data[3]<<8;
602         dataB1 = pmsg->data[4] | (u16)pmsg->data[5]<<8;
603         dataB2 = pmsg->data[6] | (u16)pmsg->data[7]<<8;
604
605         c_can_write_reg_w(pmsgobj->hostchip, dataA1, CCIF2DA1);
606         c_can_write_reg_w(pmsgobj->hostchip, dataA2, CCIF2DA2);
607         c_can_write_reg_w(pmsgobj->hostchip, dataB1, CCIF2DB1);
608         c_can_write_reg_w(pmsgobj->hostchip, dataB2, CCIF2DB2);
609      }
610
611    c_can_write_reg_w(pmsgobj->hostchip, writeSendMskCM, CCIF2CM);
612    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
613
614    spin_unlock( &c_can_if2lock );
615
616    DEBUGMSG("-> ok\n");
617 #ifdef REGDUMP
618    c_can_registerdump(pmsgobj->hostchip);
619 #endif
620
621    return 0;
622 }
623
624 //////////////////////////////////////////////////////////////////////
625 int c_can_remote_request(struct chip_t *pchip, struct msgobj_t *pmsgobj )
626 {
627    unsigned short readMaskCM = IFXCM_CNTRL;// | IFXCM_ARB;
628    //unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
629    unsigned short mcreg = 0;
630
631    DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
632
633    //Remote request is only available when the message object is in receiving mode
634    if (!can_msgobj_test_fl(pmsgobj,RX_MODE))
635      {
636         return 1;
637      }
638
639    spin_lock( &c_can_if1lock );
640
641    //loading Message Object in IF1
642    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
643    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
644    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
645    //setting Transmit-Request-Bit
646    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
647    mcreg = c_can_read_reg_w( pmsgobj->hostchip, CCIF1DMC);
648    c_can_write_reg_w(pmsgobj->hostchip, mcreg | IFXMC_TXRQST, CCIF1DMC);
649
650    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
651
652    spin_unlock( &c_can_if1lock );
653
654    DEBUGMSG("-> Sent remote request through message object %d\n", pmsgobj->object);
655 #ifdef REGDUMP
656    c_can_registerdump(pmsgobj->hostchip);
657 #endif
658
659    return 0;
660 }
661
662 ///////////////////////////////////////////////////////////////////////
663 int c_can_set_btregs(struct chip_t *pchip,
664                      u16 btr0,
665                      u16 btr1)
666 {
667    unsigned short tempCR = 0;
668
669    DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_nr);
670
671    // Validate pointer
672    if ( NULL == pchip ) return -1;
673
674    if (c_can_enable_configuration(pchip))
675      return -ENODEV;
676
677    //read Control Register
678    tempCR = c_can_read_reg_w(pchip, CCCR);
679    //Configuration Change Enable
680    c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
681    c_can_write_reg_w(pchip, btr0 | (btr1<<8), CCBT);
682
683    if (c_can_disable_configuration(pchip))
684      return -ENODEV;
685
686    DEBUGMSG("-> ok\n");
687    return 0;
688 }
689
690 ///////////////////////////////////////////////////////////////////////
691 /*
692  * Starts the Chip, by setting the CAN Enable Bit
693  */
694 int c_can_start_chip(struct chip_t *pchip)
695 {
696    u16 flags = 0;
697
698    DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_nr);
699
700    // Validate pointer
701    if ( NULL == pchip )
702      {
703         DEBUGMSG("-> Error Chip not available.\n");
704         return -1;
705      }
706
707    //   flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
708    //   c_can_write_reg_w(pchip, flags, CCCE);
709    //
710    flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
711    c_can_write_reg_w(pchip, flags, CCCE);
712
713    DEBUGMSG("-> ok\n");
714 #ifdef REGDUMP
715    c_can_registerdump(pchip);
716 #endif
717
718    return 0;
719 }
720
721 ///////////////////////////////////////////////////////////////////////
722 /*
723  * Stops the Chip, by deleting the CAN Enable Bit
724  */
725 int c_can_stop_chip(struct chip_t *pchip)
726 {
727    u16 flags = 0;
728
729    DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_nr);
730
731    // Validate pointer
732    if ( NULL == pchip )
733      {
734         DEBUGMSG("-> Error Chip not available.\n");
735         return -1;
736      }
737
738    flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
739    c_can_write_reg_w(pchip, flags, CCCE);
740
741    DEBUGMSG("-> ok\n");
742    return 0;
743 }
744
745 ///////////////////////////////////////////////////////////////////////
746 /*
747  *Check the TxOK bit of the Status Register and resets it afterwards.
748  */
749 int c_can_check_tx_stat(struct chip_t *pchip)
750 {
751    unsigned long tempstat = 0;
752
753    DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_nr);
754
755    // Validate pointer
756    if ( NULL == pchip ) return -1;
757
758    tempstat = c_can_read_reg_w(pchip, CCSR);
759
760    if (tempstat & SR_TXOK)
761      {
762         c_can_write_reg_w(pchip, tempstat & ~SR_TXOK, CCSR);
763         return 0;
764      }
765    else
766      {
767         return 1;
768      }
769 }
770
771
772 ///////////////////////////////////////////////////////////////////////
773 int c_can_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
774 {
775         can_preempt_disable();
776         
777         can_msgobj_set_fl(obj,TX_REQUEST);
778
779         /* calls i82527_irq_write_handler synchronized with other invocations
780           from kernel and IRQ context */
781         c_can_irq_sync_activities(chip, obj);
782
783         can_preempt_enable();
784         return 0;
785 }
786
787 ///////////////////////////////////////////////////////////////////////
788 int c_can_filtch_rq(struct chip_t *chip, struct msgobj_t *obj)
789 {
790         can_preempt_disable();
791         
792         can_msgobj_set_fl(obj,FILTCH_REQUEST);
793
794         /* setups filter synchronized with other invocations from kernel and IRQ context */
795         c_can_irq_sync_activities(chip, obj);
796
797         can_preempt_enable();
798         return 0;
799 }
800
801
802 ///////////////////////////////////////////////////////////////////////
803 void c_can_registerdump(struct chip_t *pchip)
804 {
805    CANMSG("------------------------------------\n");
806    CANMSG("---------C-CAN Register Dump--------\n");
807    CANMSG("------------at 0x%.8lx-----------\n"
808           ,(unsigned long)pchip->chip_base_addr);
809    CANMSG("Control Register:             0x%.4lx\n",
810           (long)(c_can_read_reg_w( pchip, CCCR)));
811    CANMSG("Status Register:              0x%.4lx\n",
812           (long)(c_can_read_reg_w( pchip, CCSR)));
813    CANMSG("Error Counting Register:      0x%.4lx\n",
814           (long)(c_can_read_reg_w( pchip, CCEC)));
815    CANMSG("Bit Timing Register:          0x%.4lx\n",
816           (long)(c_can_read_reg_w( pchip, CCBT)));
817    CANMSG("Interrupt Register:           0x%.4lx\n",
818           (long)(c_can_read_reg_w( pchip, CCINTR)));
819    CANMSG("Test Register:                0x%.4lx\n",
820           (long)(c_can_read_reg_w( pchip, CCTR)));
821    CANMSG("Baud Rate Presc. Register:    0x%.4lx\n",
822           (long)(c_can_read_reg_w( pchip, CCBRPE)));
823    CANMSG("CAN Enable Register:          0x%.4lx\n",
824           (long)(c_can_read_reg_w( pchip, CCCE)));
825    CANMSG("Transm. Req. 1 Register:      0x%.4lx\n",
826           (long)(c_can_read_reg_w( pchip, CCTREQ1)));
827    CANMSG("Transm. Req. 2 Register:      0x%.4lx\n",
828           (long)(c_can_read_reg_w( pchip, CCTREQ2)));
829    CANMSG("New Data 1 Register:          0x%.4lx\n",
830           (long)(c_can_read_reg_w( pchip, CCND1)));
831    CANMSG("New Data 2 Register:          0x%.4lx\n",
832           (long)(c_can_read_reg_w( pchip, CCND2)));
833    CANMSG("Interrupt Pend. 1 Register:   0x%.4lx\n",
834           (long)(c_can_read_reg_w( pchip, CCINTP1)));
835    CANMSG("Interrupt Pend. 2 Register:   0x%.4lx\n",
836           (long)(c_can_read_reg_w( pchip, CCINTP2)));
837    CANMSG("------------------------------------\n");
838    CANMSG("IF1 Command Req. Register:    0x%.4lx\n",
839           (long)(c_can_read_reg_w( pchip, CCIF1CR)));
840    CANMSG("IF1 Command Mask Register:    0x%.4lx\n",
841           (long)(c_can_read_reg_w( pchip, CCIF1CM)));
842    CANMSG("IF1 Mask 1 Register:          0x%.4lx\n",
843           (long)(c_can_read_reg_w( pchip, CCIF1M1)));
844    CANMSG("IF1 Mask 2 Register:          0x%.4lx\n",
845           (long)(c_can_read_reg_w( pchip, CCIF1M2)));
846    CANMSG("IF1 Arbitration 1 Register:   0x%.4lx\n",
847           (long)(c_can_read_reg_w( pchip, CCIF1A1)));
848    CANMSG("IF1 Arbitration 2 Register:   0x%.4lx\n",
849           (long)(c_can_read_reg_w( pchip, CCIF1A2)));
850    CANMSG("IF1 Message Control Register: 0x%.4lx\n",
851           (long)(c_can_read_reg_w( pchip, CCIF1DMC)));
852    CANMSG("IF1 Data A1 Register:         0x%.4lx\n",
853           (long)(c_can_read_reg_w( pchip, CCIF1DA1)));
854    CANMSG("IF1 Data A2 Register:         0x%.4lx\n",
855           (long)(c_can_read_reg_w( pchip, CCIF1DA2)));
856    CANMSG("IF1 Data B1 Register:         0x%.4lx\n",
857           (long)(c_can_read_reg_w( pchip, CCIF1DB1)));
858    CANMSG("IF1 Data B2 Register:         0x%.4lx\n",
859           (long)(c_can_read_reg_w( pchip, CCIF1DB2)));
860    CANMSG("------------------------------------\n");
861    CANMSG("IF2 Command Req. Register:    0x%.4lx\n",
862           (long)(c_can_read_reg_w( pchip, CCIF2CR)));
863    CANMSG("IF2 Command Mask Register:    0x%.4lx\n",
864           (long)(c_can_read_reg_w( pchip, CCIF2CM)));
865    CANMSG("IF2 Mask 1 Register:          0x%.4lx\n",
866           (long)(c_can_read_reg_w( pchip, CCIF2M1)));
867    CANMSG("IF2 Mask 2 Register:          0x%.4lx\n",
868           (long)(c_can_read_reg_w( pchip, CCIF2M2)));
869    CANMSG("IF2 Arbitration 1 Register:   0x%.4lx\n",
870           (long)(c_can_read_reg_w( pchip, CCIF2A1)));
871    CANMSG("IF2 Arbitration 2 Register:   0x%.4lx\n",
872           (long)(c_can_read_reg_w( pchip, CCIF2A2)));
873    CANMSG("IF2 Message Control Register: 0x%.4lx\n",
874           (long)(c_can_read_reg_w( pchip, CCIF2DMC)));
875    CANMSG("IF2 Data A1 Register:         0x%.4lx\n",
876           (long)(c_can_read_reg_w( pchip, CCIF2DA1)));
877    CANMSG("IF2 Data A2 Register:         0x%.4lx\n",
878           (long)(c_can_read_reg_w( pchip, CCIF2DA2)));
879    CANMSG("IF2 Data B1 Register:         0x%.4lx\n",
880           (long)(c_can_read_reg_w( pchip, CCIF2DB1)));
881    CANMSG("IF2 Data B2 Register:         0x%.4lx\n",
882           (long)(c_can_read_reg_w( pchip, CCIF2DB2)));
883    CANMSG("------------------------------------\n");
884    CANMSG("------------------------------------\n");
885 }
886
887 ///////////////////////////////////////////////////////////////////////
888
889 int c_can_register(struct chipspecops_t *chipspecops)
890 {
891         CANMSG("initializing c_can chip operations\n");
892         chipspecops->chip_config=c_can_chip_config;
893         chipspecops->baud_rate=c_can_baud_rate;
894         /*chipspecops->standard_mask=c_can_standard_mask;
895         chipspecops->extended_mask=c_can_extended_mask;
896         chipspecops->message15_mask=c_can_extended_mask;*/
897         chipspecops->clear_objects=c_can_clear_objects;
898         /*chipspecops->config_irqs=c_can_config_irqs;*/
899         chipspecops->pre_read_config=c_can_pre_read_config;
900         chipspecops->pre_write_config=c_can_pre_write_config;
901         chipspecops->send_msg=c_can_send_msg;
902         chipspecops->check_tx_stat=c_can_check_tx_stat;
903         chipspecops->wakeup_tx=c_can_wakeup_tx;
904         chipspecops->filtch_rq = c_can_filtch_rq;
905         chipspecops->remote_request=c_can_remote_request;
906         chipspecops->enable_configuration=c_can_enable_configuration;
907         chipspecops->disable_configuration=c_can_disable_configuration;
908         chipspecops->set_btregs=c_can_set_btregs;
909         chipspecops->start_chip=c_can_start_chip;
910         chipspecops->stop_chip=c_can_stop_chip;
911         chipspecops->irq_handler=c_can_irq_handler;
912         return 0;
913 }
914
915 /*int c_can_register(struct chip_t *pchip)
916 {
917    DEBUGMSG("(c%d)call c_can_register\n", pchip->chip_nr);
918
919    // Validate pointer
920    if ( NULL == pchip ) return -1;
921
922    pchip->chip_config = c_can_chip_config;
923    pchip->set_baud_rate = c_can_baud_rate;
924    pchip->set_mask = c_can_mask;
925    pchip->set_use_mask = c_can_use_mask;
926    //pchip->set_message15_mask = c_can_extended_mask;
927    pchip->clear_objects = c_can_clear_objects;
928    pchip->config_irqs = c_can_config_irqs;
929    pchip->pre_read_config = c_can_pre_read_config;
930    //pchip->pre_write_config = c_can_pre_write_config;
931    pchip->send_msg = c_can_send_msg;
932    pchip->check_tx_stat = c_can_check_tx_stat;
933    pchip->remote_request = c_can_remote_request;
934    pchip->enable_configuration = c_can_enable_configuration;
935    pchip->disable_configuration = c_can_disable_configuration;
936    pchip->set_btregs = c_can_set_btregs;
937    pchip->start_chip = c_can_start_chip;
938    pchip->stop_chip = c_can_stop_chip;
939    pchip->register_dump = c_can_registerdump;
940
941    DEBUGMSG("-> ok\n");
942    return 0;
943 }
944 */