lincan/src/c_can.c

   1 /**************************************************************************/
   2 /* File: c_can.c - generic C_CAN Bosch IP core handling                   */
   3 /* The C_CAN core is found in Hynix HMS30c7202 and OKI OKI ML9620 devices */
   4 /*                                                                        */
   5 /* LinCAN - (Not only) Linux CAN bus driver                               */
   6 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz>   */
   7 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz>             */
   8 /* Copyright (C) 2004 Sebastian Stolzenberg <stolzi@sebastian-stolzenberg.de> */
   9 /* Funded by OCERA and FRESCOR IST projects                               */
  10 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl>      */
  11 /* and Ake Hedman, eurosource <akhe@eurosource.se>                        */
  12 /*                                                                        */
  13 /* LinCAN is free software; you can redistribute it and/or modify it      */
  14 /* under terms of the GNU General Public License as published by the      */
  15 /* Free Software Foundation; either version 2, or (at your option) any    */
  16 /* later version.  LinCAN is distributed in the hope that it will be      */
  17 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty    */
  18 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU    */
  19 /* General Public License for more details. You should have received a    */
  20 /* copy of the GNU General Public License along with LinCAN; see file     */
  21 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave,  */
  22 /* Cambridge, MA 02139, USA.                                              */
  23 /*                                                                        */
  24 /* To allow use of LinCAN in the compact embedded systems firmware        */
  25 /* and RT-executives (RTEMS for example), main authors agree with next    */
  26 /* special exception:                                                     */
  27 /*                                                                        */
  28 /* Including LinCAN header files in a file, instantiating LinCAN generics */
  29 /* or templates, or linking other files with LinCAN objects to produce    */
  30 /* an application image/executable, does not by itself cause the          */
  31 /* resulting application image/executable to be covered by                */
  32 /* the GNU General Public License.                                        */
  33 /* This exception does not however invalidate any other reasons           */
  34 /* why the executable file might be covered by the GNU Public License.    */
  35 /* Publication of enhanced or derived LinCAN files is required although.  */
  36 /**************************************************************************/
  37
  38 #define __NO_VERSION__
  39
  40 #include "../include/can.h"
  41 #include "../include/can_sysdep.h"
  42 #include "../include/main.h"
  43 #include "../include/c_can.h"
  44
  45 extern int stdmask;
  46 extern int extmask;
  47
  48 CAN_DEFINE_SPINLOCK(c_can_spwlock);     // Spin lock for write operations
  49 CAN_DEFINE_SPINLOCK(c_can_sprlock);     // Spin lock for read operations
  50 CAN_DEFINE_SPINLOCK(c_can_if1lock);     // spin lock for the if1 register
  51 CAN_DEFINE_SPINLOCK(c_can_if2lock);     // spin lcok for the if2 register
  52
  53 /**
  54  * c_can_enable_configuration - enable chip configuration mode
  55  * @pchip: pointer to chip state structure
  56  */
  57 int c_can_enable_configuration(struct canchip_t *pchip)
  58 {
  59         int i = 0;
  60         u16 flags;
  61         DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n",
  62                  pchip->chip_idx);
  63 /*
  64    DEBUGMSG("Trying disable_irq(...) : ");
  65    //disable IRQ
  66         disable_irq(chip->chip_irq);
  67 */
  68         //read Control Register
  69         flags = c_can_read_reg_w(pchip, CCCR);
  70         //set Init-Bit in the Control Register (10 tries)
  71         while ((!(flags & CR_INIT)) && (i <= 10)) {
  72                 c_can_write_reg_w(pchip, flags | CR_INIT, CCCR);
  73                 udelay(1000);
  74                 i++;
  75                 flags = c_can_read_reg_w(pchip, CCCR);
  76         }
  77         if (i >= 10) {
  78                 CANMSG("Reset error\n");
  79                 //enable_irq(chip->chip_irq);
  80                 return -ENODEV;
  81         }
  82
  83         DEBUGMSG("-> ok\n");
  84         return 0;
  85 }
  86
  87 ///////////////////////////////////////////////////////////////////////
  88 int c_can_disable_configuration(struct canchip_t *pchip)
  89 {
  90         int i = 0;
  91         u16 flags;
  92
  93         DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n",
  94                  pchip->chip_idx);
  95         //read Control Register
  96         flags = c_can_read_reg_w(pchip, CCCR);
  97
  98         //reset Init-Bit in the Control Register (10 tries)
  99         while ((flags & CR_INIT) && (i <= 10)) {
 100                 c_can_write_reg_w(pchip, flags & ~CR_INIT, CCCR);
 101                 udelay(1000);   //100 microseconds
 102                 i++;
 103                 flags = c_can_read_reg_w(pchip, CCCR);
 104         }
 105         if (i >= 10) {
 106                 CANMSG("Error leaving reset status\n");
 107                 return -ENODEV;
 108         }
 109         //enable IRQ
 110         //enable_irq(chip->chip_irq);
 111         DEBUGMSG("-> ok\n");
 112         return 0;
 113 }
 114
 115 ///////////////////////////////////////////////////////////////////////
 116 int c_can_chip_config(struct canchip_t *pchip)
 117 {
 118
 119         DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_idx);
 120         // Validate pointer
 121         if (NULL == pchip)
 122                 return -1;
 123
 124         if (pchip->baudrate == 0)
 125                 pchip->baudrate = 1000000;
 126
 127         if (c_can_baud_rate
 128             (pchip, pchip->baudrate, pchip->clock, 0, 75, 0)) {
 129                 CANMSG("Error configuring baud rate\n");
 130                 return -ENODEV;
 131         }
 132         /*if (extended){
 133            if (c_can_extended_mask(pchip,0x0000000,extmask)) {
 134            CANMSG("Error configuring extended mask\n");
 135            return -ENODEV;
 136            }
 137            }else{
 138            if (c_can_standard_mask(pchip,0x0000,stdmask)) {
 139            CANMSG("Error configuring standard mask\n");
 140            return -ENODEV;
 141            }
 142            } */
 143         if (c_can_clear_objects(pchip)) {
 144                 CANMSG("Error clearing message objects\n");
 145                 return -ENODEV;
 146         }
 147         if (c_can_config_irqs(pchip, CR_MIE | CR_SIE | CR_EIE)) {
 148                 CANMSG("Error configuring interrupts\n");
 149                 return -ENODEV;
 150         }
 151
 152         DEBUGMSG("-> Configured successfully\n");
 153
 154 #ifdef REGDUMP
 155         c_can_registerdump(pchip);
 156 #endif
 157
 158         return 0;
 159 }
 160
 161 ///////////////////////////////////////////////////////////////////////
 162 /*
 163  * Checks if the Busy-Bit in the IF1-Command-Request Register is set
 164  */
 165 int c_can_if1_busycheck(struct canchip_t *pchip)
 166 {
 167
 168         int i = 0;
 169         unsigned short comreg = 0;
 170
 171         comreg = c_can_read_reg_w(pchip, CCIF1CR);
 172         while ((comreg & IFXCR_BUSY) && (i <= 100)) {
 173                 udelay(1);      //1 microseconds
 174                 i++;
 175                 comreg = c_can_read_reg_w(pchip, CCIF1CR);
 176         }
 177         if (i >= 10) {
 178                 CANMSG("Error Busy-Bit stays set\n");
 179                 return -ENODEV;
 180         }
 181
 182         return 0;
 183 }
 184
 185 ///////////////////////////////////////////////////////////////////////
 186 /*
 187  * Checks if the Busy-Bit in the IF2-Command-Request Register is set
 188  */
 189 int c_can_if2_busycheck(struct canchip_t *pchip)
 190 {
 191
 192         int i = 0;
 193         unsigned short comreg = 0;
 194
 195         comreg = c_can_read_reg_w(pchip, CCIF2CR);
 196         while ((comreg & IFXCR_BUSY) && (i <= 100)) {
 197                 udelay(1);      //1 microseconds
 198                 i++;
 199                 comreg = c_can_read_reg_w(pchip, CCIF2CR);
 200         }
 201         if (i >= 10) {
 202                 CANMSG("Error Busy-Bit stays set\n");
 203                 return -ENODEV;
 204         }
 205
 206         return 0;
 207 }
 208
 209 ///////////////////////////////////////////////////////////////////////
 210 /*
 211  * Though the C-CAN Chip can handle one mask for each Message Object, this Method defines
 212  * one mask for all MOs. That means every MO gets the same mask.
 213  */
 214
 215 /* Set communication parameters.
 216  * param rate baud rate in Hz
 217  * param clock frequency of C-CAN clock in Hz
 218  * param sjw synchronization jump width (0-3) prescaled clock cycles
 219  * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
 220  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
 221  */
 222 int c_can_baud_rate(struct canchip_t *pchip, int rate, int clock,
 223                     int sjw, int sampl_pt, int flags)
 224 {
 225         int best_error = 1000000000, error;
 226         int best_tseg = 0, best_brp = 0, best_rate = 0, brp = 0;
 227         int tseg = 0, tseg1 = 0, tseg2 = 0;
 228
 229         unsigned short tempCR = 0;
 230
 231         DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_idx);
 232
 233         if (c_can_enable_configuration(pchip))
 234                 return -ENODEV;
 235
 236         /* tseg even = round down, odd = round up */
 237         for (tseg = (0 + 0 + 2) * 2;
 238              tseg <= (MAX_TSEG2 + MAX_TSEG1 + 2) * 2 + 1; tseg++) {
 239                 brp = clock / ((1 + tseg / 2) * rate) + tseg % 2;
 240                 if (brp == 0 || brp > 64)
 241                         continue;
 242                 error = rate - clock / (brp * (1 + tseg / 2));
 243                 if (error < 0)
 244                         error = -error;
 245                 if (error <= best_error) {
 246                         best_error = error;
 247                         best_tseg = tseg / 2;
 248                         best_brp = brp - 1;
 249                         best_rate = clock / (brp * (1 + tseg / 2));
 250                 }
 251         }
 252         if (best_error && (rate / best_error < 10)) {
 253                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 254                        rate, clock);
 255                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 256                        best_rate, best_brp, best_tseg, tseg1, tseg2);
 257                 return -EINVAL;
 258         }
 259         tseg2 = best_tseg - (sampl_pt * (best_tseg + 1)) / 100;
 260         if (tseg2 < 0)
 261                 tseg2 = 0;
 262         if (tseg2 > MAX_TSEG2)
 263                 tseg2 = MAX_TSEG2;
 264         tseg1 = best_tseg - tseg2 - 2;
 265         if (tseg1 > MAX_TSEG1) {
 266                 tseg1 = MAX_TSEG1;
 267                 tseg2 = best_tseg - tseg1 - 2;
 268         }
 269
 270         DEBUGMSG("-> Setting %d bps.\n", best_rate);
 271         DEBUGMSG("->brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 272                  best_brp, best_tseg, tseg1, tseg2,
 273                  (100 * (best_tseg - tseg2) / (best_tseg + 1)));
 274
 275         //read Control Register
 276         tempCR = c_can_read_reg_w(pchip, CCCR);
 277         //Configuration Change Enable
 278         c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
 279         c_can_write_reg_w(pchip,
 280                           ((unsigned short)tseg2) << 12 | ((unsigned short)
 281                                                            tseg1) << 8 |
 282                           (unsigned short)sjw << 6 | (unsigned short)best_brp,
 283                           CCBT);
 284
 285         if (c_can_disable_configuration(pchip))
 286                 return -ENODEV;
 287
 288         return 0;
 289 }
 290
 291 ///////////////////////////////////////////////////////////////////////
 292 int c_can_mask(struct msgobj_t *pmsgobj, u32 mask, u16 usedirbit)
 293 {
 294         unsigned short tempreg = 0;
 295         unsigned short readMaskCM;
 296         unsigned short writeMaskCM;
 297
 298         DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n",
 299                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 300
 301         readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK;
 302         writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK | IFXCM_WRRD;
 303
 304         spin_lock(&c_can_if1lock);
 305
 306         //load Message Object in IF1
 307         if (c_can_if1_busycheck(pmsgobj->hostchip))
 308                 return -ENODEV;
 309         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 310         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 311
 312         //setting Message Valid Bit to zero
 313         if (c_can_if1_busycheck(pmsgobj->hostchip))
 314                 return -ENODEV;
 315         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 316         c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~(IFXARB2_MVAL),
 317                           CCIF1A2);
 318         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 319         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 320
 321         //setting UMask, MsgVal and Mask Register
 322         if (c_can_if1_busycheck(pmsgobj->hostchip))
 323                 return -ENODEV;
 324
 325         //set indication, that mask is used
 326         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 327         c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK,
 328                 CCIF1DMC);
 329
 330         //writing acceptance mask for extended or standart mode
 331         if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
 332                 if (usedirbit)
 333                         c_can_write_reg_w(pmsgobj->hostchip,
 334                                           (mask >> 16 & 0x1FFF) | IFXMSK2_MXTD |
 335                                           IFXMSK2_MDIR, CCIF1M2);
 336                 else
 337                         c_can_write_reg_w(pmsgobj->hostchip,
 338                                           (mask >> 16 & 0x1FFF) | IFXMSK2_MXTD,
 339                                           CCIF1M2);
 340                 c_can_write_reg_w(pmsgobj->hostchip, (mask & 0xFFFF), CCIF1M1);
 341         } else {
 342                 if (usedirbit)
 343                         c_can_write_reg_w(pmsgobj->hostchip,
 344                                           ((mask << 2) & 0x1FFC) | IFXMSK2_MDIR,
 345                                           CCIF1M2);
 346                 else
 347                         c_can_write_reg_w(pmsgobj->hostchip,
 348                                           ((mask << 2) & 0x1FFC), CCIF1M2);
 349                 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
 350         }
 351
 352         //seting Message Valid Bit to one
 353         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 354         c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
 355         //write to chip
 356         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 357         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 358
 359         spin_unlock(&c_can_if1lock);
 360
 361         DEBUGMSG("-> Setting acceptance mask to 0x%lx\n", (unsigned long)mask);
 362
 363 #ifdef REGDUMP
 364         c_can_registerdump(pmsgobj->hostchip);
 365 #endif
 366
 367         return 0;
 368 }
 369
 370 ///////////////////////////////////////////////////////////////////////
 371 int c_can_use_mask(struct msgobj_t *pmsgobj, u16 useflag)
 372 {
 373         unsigned short tempreg = 0;
 374         unsigned short readMaskCM;
 375         unsigned short writeMaskCM;
 376
 377 #ifdef DEBUG
 378         char *boolstring = "false";
 379         if (useflag)
 380                 boolstring = "true";
 381 #endif
 382         DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n",
 383                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 384
 385         readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
 386         writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;
 387
 388         spin_lock(&c_can_if1lock);
 389
 390         //load Message Object in IF1
 391         if (c_can_if1_busycheck(pmsgobj->hostchip))
 392                 return -ENODEV;
 393         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 394         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 395
 396         //setting Message Valid Bit to zero
 397         if (c_can_if1_busycheck(pmsgobj->hostchip))
 398                 return -ENODEV;
 399         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 400         c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
 401         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 402         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 403
 404         //setting UMask bit
 405         if (c_can_if1_busycheck(pmsgobj->hostchip))
 406                 return -ENODEV;
 407         if (useflag) {
 408                 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 409                 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK,
 410                                   CCIF1DMC);
 411         } else {
 412                 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 413                 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXMC_UMASK,
 414                                   CCIF1DMC);
 415         }
 416         //seting Message Valid Bit to one
 417         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 418         c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
 419         //write to chip
 420         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 421         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 422
 423         spin_unlock(&c_can_if1lock);
 424
 425 #ifdef DEBUG
 426         DEBUGMSG("-> Setting umask bit to %s\n", boolstring);
 427 #endif
 428 #ifdef REGDUMP
 429         c_can_registerdump(pmsgobj->hostchip);
 430 #endif
 431
 432         return 0;
 433 }
 434
 435 ///////////////////////////////////////////////////////////////////////
 436 int c_can_clear_objects(struct canchip_t *pchip)
 437 {
 438         unsigned short i = 0;
 439         unsigned short tempreg = 0;
 440
 441         unsigned short maskCM = IFXCM_ARB;
 442
 443         DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_idx);
 444
 445         spin_lock(&c_can_if1lock);
 446         spin_lock(&c_can_if2lock);
 447
 448         for (i = 0; i < 0x10; i++) {
 449
 450                 //loading Message Objects in IF1 and IF2
 451                 if (c_can_if1_busycheck(pchip))
 452                         return -ENODEV;
 453                 c_can_write_reg_w(pchip, maskCM, CCIF1CM);
 454                 c_can_write_reg_w(pchip, i, CCIF1CR);
 455                 if (c_can_if2_busycheck(pchip))
 456                         return -ENODEV;
 457                 c_can_write_reg_w(pchip, maskCM, CCIF2CM);
 458                 c_can_write_reg_w(pchip, i + 0x10, CCIF2CR);
 459
 460                 //setting Message Valid Bit to zero
 461                 if (c_can_if1_busycheck(pchip))
 462                         return -ENODEV;
 463                 tempreg = c_can_read_reg_w(pchip, CCIF1A2);
 464                 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
 465                 c_can_write_reg_w(pchip, i, CCIF1CR);
 466                 if (c_can_if2_busycheck(pchip))
 467                         return -ENODEV;
 468                 tempreg = c_can_read_reg_w(pchip, CCIF2A2);
 469                 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF2A2);
 470                 c_can_write_reg_w(pchip, i + 0x10, CCIF2CR);
 471         }
 472
 473         for (i = 0; i < pchip->max_objects; i++) {
 474                 if (can_msgobj_test_fl(pchip->msgobj[i], OPENED)) {
 475                         // In- and output buffer re-initialization
 476                         canqueue_ends_flush_inlist(pchip->msgobj[i]->qends);
 477                         canqueue_ends_flush_outlist(pchip->msgobj[i]->qends);
 478
 479                 }
 480         }
 481
 482         spin_unlock(&c_can_if1lock);
 483         spin_unlock(&c_can_if2lock);
 484
 485         DEBUGMSG("-> Message Objects reset\n");
 486
 487         return 0;
 488 }
 489
 490 ///////////////////////////////////////////////////////////////////////
 491 int c_can_config_irqs(struct canchip_t *pchip, u16 irqs)
 492 {
 493         u16 tempreg;
 494
 495         DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_idx);
 496
 497         tempreg = c_can_read_reg_w(pchip, CCCR);
 498         DEBUGMSG("-> CAN Control Register: 0x%4lx\n", (long)tempreg);
 499         c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
 500         DEBUGMSG("-> Configured hardware interrupt delivery\n");
 501         return 0;
 502 }
 503
 504 ///////////////////////////////////////////////////////////////////////
 505 int c_can_pre_read_config(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
 506 {
 507         unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
 508         unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
 509         unsigned short mcreg = 0;
 510         u32 id = pmsgobj->rx_preconfig_id;
 511
 512         DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n",
 513                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 514
 515         spin_lock(&c_can_if1lock);
 516
 517         if (c_can_if1_busycheck(pmsgobj->hostchip))
 518                 goto error_enodev;
 519
 520         //loading Message Object in IF1
 521         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 522         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 523
 524         if (c_can_if1_busycheck(pmsgobj->hostchip))
 525                 goto error_enodev;
 526
 527         //setting Message Valid Bit to zero
 528         c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A2);
 529         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 530         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 531
 532         /* Only access when the C_CAN controller is idle */
 533         if (c_can_if1_busycheck(pmsgobj->hostchip))
 534                 goto error_enodev;
 535
 536         //Configuring Message-Object
 537         mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 538         c_can_write_reg_w(pmsgobj->hostchip,
 539                           ((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE),
 540                           CCIF1DMC);
 541
 542         //writing arbitration mask for extended or standart mode
 543         if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
 544                 c_can_write_reg_w(pmsgobj->hostchip,
 545                                   IFXARB2_XTD | IFXARB2_MVAL | (id >> 16 &
 546                                                                 0x1FFF),
 547                                   CCIF1A2);
 548                 c_can_write_reg_w(pmsgobj->hostchip, id & 0xFFFF, CCIF1A1);
 549         } else {
 550                 c_can_write_reg_w(pmsgobj->hostchip,
 551                                   IFXARB2_MVAL | (id << 2 & 0x1FFC), CCIF1A2);
 552                 //c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
 553         }
 554         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 555         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 556
 557         spin_unlock(&c_can_if1lock);
 558
 559         DEBUGMSG("-> Receiving through message object %d with id=%d\n",
 560                  pmsgobj->object, id);
 561 #ifdef REGDUMP
 562         c_can_registerdump(pmsgobj->hostchip);
 563 #endif
 564
 565         return 0;
 566
 567       error_enodev:
 568         CANMSG("Timeout in c_can_if1_busycheck\n");
 569         spin_unlock(&c_can_if1lock);
 570         return -ENODEV;
 571
 572 }
 573
 574 ///////////////////////////////////////////////////////////////////////
 575 int c_can_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
 576                            struct canmsg_t *msg)
 577 {
 578         return 0;
 579 }
 580
 581  ///////////////////////////////////////////////////////////////////////
 582 /*
 583  *Prepare the Chip to send specified Message over specified Messageobject
 584  *In this version the method also sends the message.
 585  */
 586
 587 int c_can_send_msg(struct canchip_t *pchip, struct msgobj_t *pmsgobj,
 588                    struct canmsg_t *pmsg)
 589 {
 590         unsigned short readMaskCM =
 591             IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB;
 592         unsigned short writeMaskCM =
 593             IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB | IFXCM_WRRD;
 594         unsigned short writeSendMskCM =
 595             IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB | IFXCM_WRRD |
 596             IFXCM_TRND;
 597         unsigned short mcreg = 0;
 598         //unsigned short arbreg = 0;
 599         unsigned short dataA1 = 0;
 600         unsigned short dataA2 = 0;
 601         unsigned short dataB1 = 0;
 602         unsigned short dataB2 = 0;
 603
 604         DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n",
 605                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 606
 607         spin_lock(&c_can_if2lock);
 608
 609         can_msgobj_clear_fl(pmsgobj, RX_MODE);
 610
 611         //loading Message Object in IF1
 612         if (c_can_if2_busycheck(pmsgobj->hostchip))
 613                 return -ENODEV;
 614         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF2CM);
 615         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
 616         //setting Message Valid Bit to zero
 617         if (c_can_if2_busycheck(pmsgobj->hostchip))
 618                 return -ENODEV;
 619         c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF2A2);
 620         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF2CM);
 621         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
 622         //Configuring MO
 623         if (c_can_if2_busycheck(pmsgobj->hostchip))
 624                 return -ENODEV;
 625         mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF2CM);
 626         //remote enable?
 627         //define Command Mask
 628         c_can_write_reg_w(pmsgobj->hostchip,
 629                           (mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_TXIE |
 630                           IFXMC_RMTEN | IFXMC_NEWDAT | IFXMC_TXRQST | (pmsg->
 631                                                                        length &
 632                                                                        0xF),
 633                           CCIF2DMC);
 634         //set Arbitration Bits
 635         if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
 636                 c_can_write_reg_w(pmsgobj->hostchip, (u16) (pmsg->id), CCIF2A1);
 637                 c_can_write_reg_w(pmsgobj->hostchip,
 638                                   IFXARB2_XTD | IFXARB2_MVAL | IFXARB2_DIR |
 639                                   ((u16) (pmsg->id >> 16) & 0x1FFF), CCIF2A2);
 640         } else {
 641                 c_can_write_reg_w(pmsgobj->hostchip,
 642                                   (IFXARB2_MVAL | IFXARB2_DIR |
 643                                    ((u16) (pmsg->id << 2) & 0x1FFC)), CCIF2A2);
 644                 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
 645         }
 646         //write Data
 647         if (pmsg->length > 0) {
 648                 dataA1 = pmsg->data[0] | (u16) pmsg->data[1] << 8;
 649                 dataA2 = pmsg->data[2] | (u16) pmsg->data[3] << 8;
 650                 dataB1 = pmsg->data[4] | (u16) pmsg->data[5] << 8;
 651                 dataB2 = pmsg->data[6] | (u16) pmsg->data[7] << 8;
 652
 653                 c_can_write_reg_w(pmsgobj->hostchip, dataA1, CCIF2DA1);
 654                 c_can_write_reg_w(pmsgobj->hostchip, dataA2, CCIF2DA2);
 655                 c_can_write_reg_w(pmsgobj->hostchip, dataB1, CCIF2DB1);
 656                 c_can_write_reg_w(pmsgobj->hostchip, dataB2, CCIF2DB2);
 657         }
 658
 659         c_can_write_reg_w(pmsgobj->hostchip, writeSendMskCM, CCIF2CM);
 660         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
 661
 662         spin_unlock(&c_can_if2lock);
 663
 664         DEBUGMSG("-> ok\n");
 665 #ifdef REGDUMP
 666         c_can_registerdump(pmsgobj->hostchip);
 667 #endif
 668
 669         return 0;
 670 }
 671
 672 //////////////////////////////////////////////////////////////////////
 673 int c_can_remote_request(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
 674 {
 675         unsigned short readMaskCM = IFXCM_CNTRL;        // | IFXCM_ARB;
 676         //unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
 677         unsigned short mcreg = 0;
 678
 679         DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n",
 680                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 681
 682         //Remote request is only available when the message object is in receiving mode
 683         if (!can_msgobj_test_fl(pmsgobj, RX_MODE)) {
 684                 return 1;
 685         }
 686
 687         spin_lock(&c_can_if1lock);
 688
 689         //loading Message Object in IF1
 690         if (c_can_if1_busycheck(pmsgobj->hostchip))
 691                 return -ENODEV;
 692         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 693         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 694         //setting Transmit-Request-Bit
 695         if (c_can_if1_busycheck(pmsgobj->hostchip))
 696                 return -ENODEV;
 697         mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 698         c_can_write_reg_w(pmsgobj->hostchip, mcreg | IFXMC_TXRQST, CCIF1DMC);
 699
 700         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 701
 702         spin_unlock(&c_can_if1lock);
 703
 704         DEBUGMSG("-> Sent remote request through message object %d\n",
 705                  pmsgobj->object);
 706 #ifdef REGDUMP
 707         c_can_registerdump(pmsgobj->hostchip);
 708 #endif
 709
 710         return 0;
 711 }
 712
 713 ///////////////////////////////////////////////////////////////////////
 714 int c_can_set_btregs(struct canchip_t *pchip, u16 btr0, u16 btr1)
 715 {
 716         unsigned short tempCR = 0;
 717
 718         DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_idx);
 719
 720         // Validate pointer
 721         if (NULL == pchip)
 722                 return -1;
 723
 724         if (c_can_enable_configuration(pchip))
 725                 return -ENODEV;
 726
 727         //read Control Register
 728         tempCR = c_can_read_reg_w(pchip, CCCR);
 729         //Configuration Change Enable
 730         c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
 731         c_can_write_reg_w(pchip, btr0 | (btr1 << 8), CCBT);
 732
 733         if (c_can_disable_configuration(pchip))
 734                 return -ENODEV;
 735
 736         DEBUGMSG("-> ok\n");
 737         return 0;
 738 }
 739
 740 ///////////////////////////////////////////////////////////////////////
 741 /*
 742  * Starts the Chip, by setting the CAN Enable Bit
 743  */
 744 int c_can_start_chip(struct canchip_t *pchip)
 745 {
 746         u16 flags = 0;
 747
 748         DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_idx);
 749
 750         // Validate pointer
 751         if (NULL == pchip) {
 752                 DEBUGMSG("-> Error Chip not available.\n");
 753                 return -1;
 754         }
 755 #ifdef C_CAN_WITH_CCCE
 756         flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
 757         c_can_write_reg_w(pchip, flags, CCCE);
 758 #endif
 759
 760         DEBUGMSG("-> ok\n");
 761 #ifdef REGDUMP
 762         c_can_registerdump(pchip);
 763 #endif
 764
 765         return 0;
 766 }
 767
 768 ///////////////////////////////////////////////////////////////////////
 769 /*
 770  * Stops the Chip, by deleting the CAN Enable Bit
 771  */
 772 int c_can_stop_chip(struct canchip_t *pchip)
 773 {
 774         u16 flags = 0;
 775
 776         DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_idx);
 777
 778         // Validate pointer
 779         if (NULL == pchip) {
 780                 DEBUGMSG("-> Error Chip not available.\n");
 781                 return -1;
 782         }
 783 #ifdef C_CAN_WITH_CCCE
 784         flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
 785         c_can_write_reg_w(pchip, flags, CCCE);
 786 #endif
 787
 788         DEBUGMSG("-> ok\n");
 789         return 0;
 790 }
 791
 792 int c_can_attach_to_chip(struct canchip_t *chip)
 793 {
 794         return 0;
 795 }
 796
 797 int c_can_release_chip(struct canchip_t *chip)
 798 {
 799         int temp;
 800
 801         temp = c_can_read_reg_w(chip, CCCR);
 802
 803         /* Disable IRQ generation */
 804         c_can_config_irqs(chip, 0);
 805
 806         temp = c_can_read_reg_w(chip, CCCR);
 807
 808         /* Power-down C_CAN, except this does nothing in the version 1.2 */
 809         c_can_stop_chip(chip);
 810
 811         return 0;
 812 }
 813
 814 ///////////////////////////////////////////////////////////////////////
 815 /*
 816  *Check the TxOK bit of the Status Register and resets it afterwards.
 817  */
 818 int c_can_check_tx_stat(struct canchip_t *pchip)
 819 {
 820         unsigned long tempstat = 0;
 821
 822         DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_idx);
 823
 824         // Validate pointer
 825         if (NULL == pchip)
 826                 return -1;
 827
 828         tempstat = c_can_read_reg_w(pchip, CCSR);
 829
 830         if (tempstat & SR_TXOK) {
 831                 c_can_write_reg_w(pchip, tempstat & ~SR_TXOK, CCSR);
 832                 return 0;
 833         } else {
 834                 return 1;
 835         }
 836 }
 837
 838 ///////////////////////////////////////////////////////////////////////
 839 int c_can_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
 840 {
 841         can_preempt_disable();
 842
 843         can_msgobj_set_fl(obj, TX_REQUEST);
 844
 845         /* calls c_can_irq_write_handler synchronized with other invocations
 846            from kernel and IRQ context */
 847         c_can_irq_sync_activities(chip, obj);
 848
 849         can_preempt_enable();
 850         return 0;
 851 }
 852
 853 ///////////////////////////////////////////////////////////////////////
 854 int c_can_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
 855 {
 856         can_preempt_disable();
 857
 858         can_msgobj_set_fl(obj, FILTCH_REQUEST);
 859
 860         /* setups filter synchronized with other invocations from kernel and IRQ context */
 861         c_can_irq_sync_activities(chip, obj);
 862
 863         can_preempt_enable();
 864         return 0;
 865 }
 866
 867 ///////////////////////////////////////////////////////////////////////
 868 void c_can_registerdump(struct canchip_t *pchip)
 869 {
 870         CANMSG("------------------------------------\n");
 871         CANMSG("---------C-CAN Register Dump--------\n");
 872         CANMSG("------------at 0x%.8lx-----------\n",
 873                (unsigned long)pchip->chip_base_addr);
 874         CANMSG("Control Register:             0x%.4lx\n",
 875                (long)(c_can_read_reg_w(pchip, CCCR)));
 876         CANMSG("Status Register:              0x%.4lx\n",
 877                (long)(c_can_read_reg_w(pchip, CCSR)));
 878         CANMSG("Error Counting Register:      0x%.4lx\n",
 879                (long)(c_can_read_reg_w(pchip, CCEC)));
 880         CANMSG("Bit Timing Register:          0x%.4lx\n",
 881                (long)(c_can_read_reg_w(pchip, CCBT)));
 882         CANMSG("Interrupt Register:           0x%.4lx\n",
 883                (long)(c_can_read_reg_w(pchip, CCINTR)));
 884         CANMSG("Test Register:                0x%.4lx\n",
 885                (long)(c_can_read_reg_w(pchip, CCTR)));
 886         CANMSG("Baud Rate Presc. Register:    0x%.4lx\n",
 887                (long)(c_can_read_reg_w(pchip, CCBRPE)));
 888 #ifdef C_CAN_WITH_CCCE
 889         CANMSG("CAN Enable Register:          0x%.4lx\n",
 890                (long)(c_can_read_reg_w(pchip, CCCE)));
 891 #endif
 892         CANMSG("Transm. Req. 1 Register:      0x%.4lx\n",
 893                (long)(c_can_read_reg_w(pchip, CCTREQ1)));
 894         CANMSG("Transm. Req. 2 Register:      0x%.4lx\n",
 895                (long)(c_can_read_reg_w(pchip, CCTREQ2)));
 896         CANMSG("New Data 1 Register:          0x%.4lx\n",
 897                (long)(c_can_read_reg_w(pchip, CCND1)));
 898         CANMSG("New Data 2 Register:          0x%.4lx\n",
 899                (long)(c_can_read_reg_w(pchip, CCND2)));
 900         CANMSG("Interrupt Pend. 1 Register:   0x%.4lx\n",
 901                (long)(c_can_read_reg_w(pchip, CCINTP1)));
 902         CANMSG("Interrupt Pend. 2 Register:   0x%.4lx\n",
 903                (long)(c_can_read_reg_w(pchip, CCINTP2)));
 904         CANMSG("------------------------------------\n");
 905         CANMSG("IF1 Command Req. Register:    0x%.4lx\n",
 906                (long)(c_can_read_reg_w(pchip, CCIF1CR)));
 907         CANMSG("IF1 Command Mask Register:    0x%.4lx\n",
 908                (long)(c_can_read_reg_w(pchip, CCIF1CM)));
 909         CANMSG("IF1 Mask 1 Register:          0x%.4lx\n",
 910                (long)(c_can_read_reg_w(pchip, CCIF1M1)));
 911         CANMSG("IF1 Mask 2 Register:          0x%.4lx\n",
 912                (long)(c_can_read_reg_w(pchip, CCIF1M2)));
 913         CANMSG("IF1 Arbitration 1 Register:   0x%.4lx\n",
 914                (long)(c_can_read_reg_w(pchip, CCIF1A1)));
 915         CANMSG("IF1 Arbitration 2 Register:   0x%.4lx\n",
 916                (long)(c_can_read_reg_w(pchip, CCIF1A2)));
 917         CANMSG("IF1 Message Control Register: 0x%.4lx\n",
 918                (long)(c_can_read_reg_w(pchip, CCIF1DMC)));
 919         CANMSG("IF1 Data A1 Register:         0x%.4lx\n",
 920                (long)(c_can_read_reg_w(pchip, CCIF1DA1)));
 921         CANMSG("IF1 Data A2 Register:         0x%.4lx\n",
 922                (long)(c_can_read_reg_w(pchip, CCIF1DA2)));
 923         CANMSG("IF1 Data B1 Register:         0x%.4lx\n",
 924                (long)(c_can_read_reg_w(pchip, CCIF1DB1)));
 925         CANMSG("IF1 Data B2 Register:         0x%.4lx\n",
 926                (long)(c_can_read_reg_w(pchip, CCIF1DB2)));
 927         CANMSG("------------------------------------\n");
 928         CANMSG("IF2 Command Req. Register:    0x%.4lx\n",
 929                (long)(c_can_read_reg_w(pchip, CCIF2CR)));
 930         CANMSG("IF2 Command Mask Register:    0x%.4lx\n",
 931                (long)(c_can_read_reg_w(pchip, CCIF2CM)));
 932         CANMSG("IF2 Mask 1 Register:          0x%.4lx\n",
 933                (long)(c_can_read_reg_w(pchip, CCIF2M1)));
 934         CANMSG("IF2 Mask 2 Register:          0x%.4lx\n",
 935                (long)(c_can_read_reg_w(pchip, CCIF2M2)));
 936         CANMSG("IF2 Arbitration 1 Register:   0x%.4lx\n",
 937                (long)(c_can_read_reg_w(pchip, CCIF2A1)));
 938         CANMSG("IF2 Arbitration 2 Register:   0x%.4lx\n",
 939                (long)(c_can_read_reg_w(pchip, CCIF2A2)));
 940         CANMSG("IF2 Message Control Register: 0x%.4lx\n",
 941                (long)(c_can_read_reg_w(pchip, CCIF2DMC)));
 942         CANMSG("IF2 Data A1 Register:         0x%.4lx\n",
 943                (long)(c_can_read_reg_w(pchip, CCIF2DA1)));
 944         CANMSG("IF2 Data A2 Register:         0x%.4lx\n",
 945                (long)(c_can_read_reg_w(pchip, CCIF2DA2)));
 946         CANMSG("IF2 Data B1 Register:         0x%.4lx\n",
 947                (long)(c_can_read_reg_w(pchip, CCIF2DB1)));
 948         CANMSG("IF2 Data B2 Register:         0x%.4lx\n",
 949                (long)(c_can_read_reg_w(pchip, CCIF2DB2)));
 950         CANMSG("------------------------------------\n");
 951         CANMSG("------------------------------------\n");
 952 }
 953
 954 void c_can_if1_registerdump(struct canchip_t *pchip)
 955 {
 956         CANMSG("----------------------------------------\n");
 957         CANMSG("Error Counting Register:      0x%.4lx\n",
 958                (long)(c_can_read_reg_w(pchip, CCEC)));
 959         CANMSG("---------C-CAN IF1 Register Dump--------\n");
 960         CANMSG("IF1 Command Req. Register:    0x%.4lx\n",
 961                (long)(c_can_read_reg_w(pchip, CCIF1CR)));
 962         CANMSG("IF1 Command Mask Register:    0x%.4lx\n",
 963                (long)(c_can_read_reg_w(pchip, CCIF1CM)));
 964         CANMSG("IF1 Mask 1 Register:          0x%.4lx\n",
 965                (long)(c_can_read_reg_w(pchip, CCIF1M1)));
 966         CANMSG("IF1 Mask 2 Register:          0x%.4lx\n",
 967                (long)(c_can_read_reg_w(pchip, CCIF1M2)));
 968         CANMSG("IF1 Arbitration 1 Register:   0x%.4lx\n",
 969                (long)(c_can_read_reg_w(pchip, CCIF1A1)));
 970         CANMSG("IF1 Arbitration 2 Register:   0x%.4lx\n",
 971                (long)(c_can_read_reg_w(pchip, CCIF1A2)));
 972         CANMSG("IF1 Message Control Register: 0x%.4lx\n",
 973                (long)(c_can_read_reg_w(pchip, CCIF1DMC)));
 974         CANMSG("IF1 Data A1 Register:         0x%.4lx\n",
 975                (long)(c_can_read_reg_w(pchip, CCIF1DA1)));
 976         CANMSG("IF1 Data A2 Register:         0x%.4lx\n",
 977                (long)(c_can_read_reg_w(pchip, CCIF1DA2)));
 978         CANMSG("IF1 Data B1 Register:         0x%.4lx\n",
 979                (long)(c_can_read_reg_w(pchip, CCIF1DB1)));
 980         CANMSG("IF1 Data B2 Register:         0x%.4lx\n",
 981                (long)(c_can_read_reg_w(pchip, CCIF1DB2)));
 982 }
 983
 984 ///////////////////////////////////////////////////////////////////////
 985
 986 int c_can_register(struct chipspecops_t *chipspecops)
 987 {
 988         CANMSG("initializing c_can chip operations\n");
 989         chipspecops->chip_config = c_can_chip_config;
 990         chipspecops->baud_rate = c_can_baud_rate;
 991         /*chipspecops->standard_mask=c_can_standard_mask;
 992            chipspecops->extended_mask=c_can_extended_mask;
 993            chipspecops->message15_mask=c_can_extended_mask; */
 994         chipspecops->clear_objects = c_can_clear_objects;
 995         /*chipspecops->config_irqs=c_can_config_irqs; */
 996         chipspecops->pre_read_config = c_can_pre_read_config;
 997         chipspecops->pre_write_config = c_can_pre_write_config;
 998         chipspecops->send_msg = c_can_send_msg;
 999         chipspecops->check_tx_stat = c_can_check_tx_stat;
1000         chipspecops->wakeup_tx = c_can_wakeup_tx;
1001         chipspecops->filtch_rq = c_can_filtch_rq;
1002         chipspecops->remote_request = c_can_remote_request;
1003         chipspecops->enable_configuration = c_can_enable_configuration;
1004         chipspecops->disable_configuration = c_can_disable_configuration;
1005         chipspecops->attach_to_chip = c_can_attach_to_chip;
1006         chipspecops->release_chip = c_can_release_chip;
1007         chipspecops->set_btregs = c_can_set_btregs;
1008         chipspecops->start_chip = c_can_start_chip;
1009         chipspecops->stop_chip = c_can_stop_chip;
1010         chipspecops->irq_handler = c_can_irq_handler;
1011         chipspecops->irq_accept = NULL;
1012         return 0;
1013 }
1014
1015 int c_can_fill_chipspecops(struct canchip_t *chip)
1016 {
1017         chip->chip_type = "c_can";
1018         if (MAX_MSGOBJS >= 32) {
1019                 chip->max_objects = 32;
1020         } else {
1021                 CANMSG("C_CAN requires 32 message objects per chip,"
1022                        " but only %d is compiled maximum\n", MAX_MSGOBJS);
1023                 chip->max_objects = MAX_MSGOBJS;
1024         }
1025         c_can_register(chip->chipspecops);
1026         return 0;
1027 }