1 /* c_can.c - Hynix HMS30c7202 ARM generic C_CAN module handling
2 * Linux CAN-bus device driver.
3 * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de
4 * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl
5 * and Ake Hedman, eurosource, akhe@eurosource.se
6 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
7 * email:pisa@cmp.felk.cvut.cz
8 * This software is released under the GPL-License.
9 * Version lincan-0.3 17 Jun 2004
12 #define __NO_VERSION__
14 #include "../include/can.h"
15 #include "../include/can_sysdep.h"
16 #include "../include/main.h"
17 #include "../include/c_can.h"
22 CAN_DEFINE_SPINLOCK(c_can_spwlock); // Spin lock for write operations
23 CAN_DEFINE_SPINLOCK(c_can_sprlock); // Spin lock for read operations
24 CAN_DEFINE_SPINLOCK(c_can_if1lock); // spin lock for the if1 register
25 CAN_DEFINE_SPINLOCK(c_can_if2lock); // spin lcok for the if2 register
28 * c_can_enable_configuration - enable chip configuration mode
29 * @pchip: pointer to chip state structure
31 int c_can_enable_configuration(struct canchip_t *pchip)
35 DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n",
38 DEBUGMSG("Trying disable_irq(...) : ");
40 disable_irq(chip->chip_irq);
42 //read Control Register
43 flags = c_can_read_reg_w(pchip, CCCR);
44 //set Init-Bit in the Control Register (10 tries)
45 while ((!(flags & CR_INIT)) && (i <= 10)) {
46 c_can_write_reg_w(pchip, flags | CR_INIT, CCCR);
49 flags = c_can_read_reg_w(pchip, CCCR);
52 CANMSG("Reset error\n");
53 //enable_irq(chip->chip_irq);
61 ///////////////////////////////////////////////////////////////////////
62 int c_can_disable_configuration(struct canchip_t *pchip)
67 DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n",
69 //read Control Register
70 flags = c_can_read_reg_w(pchip, CCCR);
72 //reset Init-Bit in the Control Register (10 tries)
73 while ((flags & CR_INIT) && (i <= 10)) {
74 c_can_write_reg_w(pchip, flags & ~CR_INIT, CCCR);
75 udelay(1000); //100 microseconds
77 flags = c_can_read_reg_w(pchip, CCCR);
80 CANMSG("Error leaving reset status\n");
84 //enable_irq(chip->chip_irq);
89 ///////////////////////////////////////////////////////////////////////
90 int c_can_chip_config(struct canchip_t *pchip)
93 DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_idx);
98 if (pchip->baudrate == 0)
99 pchip->baudrate = 1000;
102 (pchip, pchip->baudrate * 1000, pchip->clock, 0, 75, 0)) {
103 CANMSG("Error configuring baud rate\n");
107 if (c_can_extended_mask(pchip,0x0000000,extmask)) {
108 CANMSG("Error configuring extended mask\n");
112 if (c_can_standard_mask(pchip,0x0000,stdmask)) {
113 CANMSG("Error configuring standard mask\n");
117 if (c_can_clear_objects(pchip)) {
118 CANMSG("Error clearing message objects\n");
121 if (c_can_config_irqs(pchip, CR_MIE | CR_SIE | CR_EIE)) {
122 CANMSG("Error configuring interrupts\n");
126 DEBUGMSG("-> Configured successfully\n");
129 c_can_registerdump(pchip);
135 ///////////////////////////////////////////////////////////////////////
137 * Checks if the Busy-Bit in the IF1-Command-Request Register is set
139 int c_can_if1_busycheck(struct canchip_t *pchip)
143 unsigned short comreg = 0;
145 comreg = c_can_read_reg_w(pchip, CCIF1CR);
146 while ((comreg & IFXCR_BUSY) && (i <= 10)) {
147 udelay(100); //100 microseconds
149 comreg = c_can_read_reg_w(pchip, CCIF1CR);
152 CANMSG("Error Busy-Bit stays set\n");
159 ///////////////////////////////////////////////////////////////////////
161 * Checks if the Busy-Bit in the IF2-Command-Request Register is set
163 int c_can_if2_busycheck(struct canchip_t *pchip)
167 unsigned short comreg = 0;
169 comreg = c_can_read_reg_w(pchip, CCIF2CR);
170 while ((comreg & IFXCR_BUSY) && (i <= 10)) {
171 udelay(100); //100 microseconds
173 comreg = c_can_read_reg_w(pchip, CCIF2CR);
176 CANMSG("Error Busy-Bit stays set\n");
183 ///////////////////////////////////////////////////////////////////////
185 * Though the C-CAN Chip can handle one mask for each Message Object, this Method defines
186 * one mask for all MOs. That means every MO gets the same mask.
189 /* Set communication parameters.
190 * param rate baud rate in Hz
191 * param clock frequency of C-CAN clock in Hz
192 * param sjw synchronization jump width (0-3) prescaled clock cycles
193 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
194 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
196 int c_can_baud_rate(struct canchip_t *pchip, int rate, int clock,
197 int sjw, int sampl_pt, int flags)
199 int best_error = 1000000000, error;
200 int best_tseg = 0, best_brp = 0, best_rate = 0, brp = 0;
201 int tseg = 0, tseg1 = 0, tseg2 = 0;
203 unsigned short tempCR = 0;
205 DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_idx);
207 if (c_can_enable_configuration(pchip))
210 /* tseg even = round down, odd = round up */
211 for (tseg = (0 + 0 + 2) * 2;
212 tseg <= (MAX_TSEG2 + MAX_TSEG1 + 2) * 2 + 1; tseg++) {
213 brp = clock / ((1 + tseg / 2) * rate) + tseg % 2;
214 if (brp == 0 || brp > 64)
216 error = rate - clock / (brp * (1 + tseg / 2));
219 if (error <= best_error) {
221 best_tseg = tseg / 2;
223 best_rate = clock / (brp * (1 + tseg / 2));
226 if (best_error && (rate / best_error < 10)) {
227 CANMSG("baud rate %d is not possible with %d Hz clock\n",
229 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
230 best_rate, best_brp, best_tseg, tseg1, tseg2);
233 tseg2 = best_tseg - (sampl_pt * (best_tseg + 1)) / 100;
236 if (tseg2 > MAX_TSEG2)
238 tseg1 = best_tseg - tseg2 - 2;
239 if (tseg1 > MAX_TSEG1) {
241 tseg2 = best_tseg - tseg1 - 2;
244 DEBUGMSG("-> Setting %d bps.\n", best_rate);
245 DEBUGMSG("->brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
246 best_brp, best_tseg, tseg1, tseg2,
247 (100 * (best_tseg - tseg2) / (best_tseg + 1)));
249 //read Control Register
250 tempCR = c_can_read_reg_w(pchip, CCCR);
251 //Configuration Change Enable
252 c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
253 c_can_write_reg_w(pchip,
254 ((unsigned short)tseg2) << 12 | ((unsigned short)
256 (unsigned short)sjw << 6 | (unsigned short)best_brp,
259 if (c_can_disable_configuration(pchip))
265 ///////////////////////////////////////////////////////////////////////
266 int c_can_mask(struct msgobj_t *pmsgobj, u32 mask, u16 usedirbit)
268 unsigned short tempreg = 0;
269 unsigned short readMaskCM;
270 unsigned short writeMaskCM;
272 DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n",
273 pmsgobj->hostchip->chip_idx, pmsgobj->object);
275 readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK;
276 writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK | IFXCM_WRRD;
278 spin_lock(&c_can_if1lock);
280 //load Message Object in IF1
281 if (c_can_if1_busycheck(pmsgobj->hostchip))
283 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
284 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
286 //setting Message Valid Bit to zero
287 if (c_can_if1_busycheck(pmsgobj->hostchip))
289 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
290 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~(IFXARB2_MVAL),
292 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
293 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
295 //setting UMask, MsgVal and Mask Register
296 if (c_can_if1_busycheck(pmsgobj->hostchip))
299 //writing acceptance mask for extended or standart mode
300 if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
302 c_can_write_reg_w(pmsgobj->hostchip,
303 (mask >> 16 & 0x1FFF) | IFXMSK2_MXTD |
304 IFXMSK2_MDIR, CCIF1M2);
306 c_can_write_reg_w(pmsgobj->hostchip,
307 (mask >> 16 & 0x1FFF) | IFXMSK2_MXTD,
309 c_can_write_reg_w(pmsgobj->hostchip, (mask & 0xFFFF), CCIF1M1);
312 c_can_write_reg_w(pmsgobj->hostchip,
313 ((mask << 2) & 0x1FFC) | IFXMSK2_MDIR,
316 c_can_write_reg_w(pmsgobj->hostchip,
317 ((mask << 2) & 0x1FFC), CCIF1M2);
318 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
320 //seting Message Valid Bit to one
321 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
322 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
324 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
325 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
327 spin_unlock(&c_can_if1lock);
329 DEBUGMSG("-> Setting acceptance mask to 0x%lx\n", (unsigned long)mask);
332 c_can_registerdump(pmsgobj->hostchip);
338 ///////////////////////////////////////////////////////////////////////
339 int c_can_use_mask(struct msgobj_t *pmsgobj, u16 useflag)
341 unsigned short tempreg = 0;
342 unsigned short readMaskCM;
343 unsigned short writeMaskCM;
346 char *boolstring = "false";
350 DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n",
351 pmsgobj->hostchip->chip_idx, pmsgobj->object);
353 readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
354 writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;
356 spin_lock(&c_can_if1lock);
358 //load Message Object in IF1
359 if (c_can_if1_busycheck(pmsgobj->hostchip))
361 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
362 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
364 //setting Message Valid Bit to zero
365 if (c_can_if1_busycheck(pmsgobj->hostchip))
367 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
368 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
369 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
370 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
373 if (c_can_if1_busycheck(pmsgobj->hostchip))
376 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
377 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK,
380 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
381 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXMC_UMASK,
384 //seting Message Valid Bit to one
385 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
386 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
388 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
389 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
391 spin_unlock(&c_can_if1lock);
394 DEBUGMSG("-> Setting umask bit to %s\n", boolstring);
397 c_can_registerdump(pmsgobj->hostchip);
403 ///////////////////////////////////////////////////////////////////////
404 int c_can_clear_objects(struct canchip_t *pchip)
406 unsigned short i = 0;
407 unsigned short tempreg = 0;
409 unsigned short maskCM = IFXCM_ARB;
411 DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_idx);
413 spin_lock(&c_can_if1lock);
414 spin_lock(&c_can_if2lock);
416 for (i = 0; i < 0x10; i++) {
418 //loading Message Objects in IF1 and IF2
419 if (c_can_if1_busycheck(pchip))
421 c_can_write_reg_w(pchip, maskCM, CCIF1CM);
422 c_can_write_reg_w(pchip, i, CCIF1CR);
423 if (c_can_if2_busycheck(pchip))
425 c_can_write_reg_w(pchip, maskCM, CCIF2CM);
426 c_can_write_reg_w(pchip, i + 0x10, CCIF2CR);
428 //setting Message Valid Bit to zero
429 if (c_can_if1_busycheck(pchip))
431 tempreg = c_can_read_reg_w(pchip, CCIF1A2);
432 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
433 c_can_write_reg_w(pchip, i, CCIF1CR);
434 if (c_can_if2_busycheck(pchip))
436 tempreg = c_can_read_reg_w(pchip, CCIF2A2);
437 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF2A2);
438 c_can_write_reg_w(pchip, i + 0x10, CCIF2CR);
441 for (i = 0; i < pchip->max_objects; i++) {
442 if (can_msgobj_test_fl(pchip->msgobj[i], OPENED)) {
443 // In- and output buffer re-initialization
444 canqueue_ends_flush_inlist(pchip->msgobj[i]->qends);
445 canqueue_ends_flush_outlist(pchip->msgobj[i]->qends);
450 spin_unlock(&c_can_if1lock);
451 spin_unlock(&c_can_if2lock);
453 DEBUGMSG("-> Message Objects reset\n");
458 ///////////////////////////////////////////////////////////////////////
459 int c_can_config_irqs(struct canchip_t *pchip, u16 irqs)
463 DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_idx);
465 tempreg = c_can_read_reg_w(pchip, CCCR);
466 DEBUGMSG("-> CAN Control Register: 0x%4lx\n", (long)tempreg);
467 c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
468 DEBUGMSG("-> Configured hardware interrupt delivery\n");
472 ///////////////////////////////////////////////////////////////////////
473 int c_can_pre_read_config(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
475 unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
476 unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
477 unsigned short mcreg = 0;
478 u32 id = pmsgobj->rx_preconfig_id;
480 DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n",
481 pmsgobj->hostchip->chip_idx, pmsgobj->object);
483 spin_lock(&c_can_if1lock);
485 if (c_can_if1_busycheck(pmsgobj->hostchip))
488 //loading Message Object in IF1
489 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
490 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
492 if (c_can_if1_busycheck(pmsgobj->hostchip))
495 //setting Message Valid Bit to zero
496 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A2);
497 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
498 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
500 /* Only access when the C_CAN controller is idle */
501 if (c_can_if1_busycheck(pmsgobj->hostchip))
504 //Configuring Message-Object
505 mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
506 c_can_write_reg_w(pmsgobj->hostchip,
507 ((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE),
510 //writing arbitration mask for extended or standart mode
511 if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
512 c_can_write_reg_w(pmsgobj->hostchip,
513 IFXARB2_XTD | IFXARB2_MVAL | (id >> 16 &
516 c_can_write_reg_w(pmsgobj->hostchip, id & 0xFFFF, CCIF1A1);
518 c_can_write_reg_w(pmsgobj->hostchip,
519 IFXARB2_MVAL | (id << 2 & 0x1FFC), CCIF1A2);
520 //c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
522 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
523 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
525 spin_unlock(&c_can_if1lock);
527 DEBUGMSG("-> Receiving through message object %d with id=%d\n",
528 pmsgobj->object, id);
530 c_can_registerdump(pmsgobj->hostchip);
536 CANMSG("Timeout in c_can_if1_busycheck\n");
537 spin_unlock(&c_can_if1lock);
542 ///////////////////////////////////////////////////////////////////////
543 int c_can_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
544 struct canmsg_t *msg)
549 ///////////////////////////////////////////////////////////////////////
551 *Prepare the Chip to send specified Message over specified Messageobject
552 *In this version the method also sends the message.
555 int c_can_send_msg(struct canchip_t *pchip, struct msgobj_t *pmsgobj,
556 struct canmsg_t *pmsg)
558 unsigned short readMaskCM =
559 IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB;
560 unsigned short writeMaskCM =
561 IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB | IFXCM_WRRD;
562 unsigned short writeSendMskCM =
563 IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB | IFXCM_WRRD |
565 unsigned short mcreg = 0;
566 //unsigned short arbreg = 0;
567 unsigned short dataA1 = 0;
568 unsigned short dataA2 = 0;
569 unsigned short dataB1 = 0;
570 unsigned short dataB2 = 0;
572 DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n",
573 pmsgobj->hostchip->chip_idx, pmsgobj->object);
575 spin_lock(&c_can_if2lock);
577 can_msgobj_clear_fl(pmsgobj, RX_MODE);
579 //loading Message Object in IF1
580 if (c_can_if2_busycheck(pmsgobj->hostchip))
582 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF2CM);
583 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
584 //setting Message Valid Bit to zero
585 if (c_can_if2_busycheck(pmsgobj->hostchip))
587 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF2A2);
588 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF2CM);
589 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
591 if (c_can_if2_busycheck(pmsgobj->hostchip))
593 mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF2CM);
595 //define Command Mask
596 c_can_write_reg_w(pmsgobj->hostchip,
597 (mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_TXIE |
598 IFXMC_RMTEN | IFXMC_NEWDAT | IFXMC_TXRQST | (pmsg->
602 //set Arbitration Bits
603 if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
604 c_can_write_reg_w(pmsgobj->hostchip, (u16) (pmsg->id), CCIF2A1);
605 c_can_write_reg_w(pmsgobj->hostchip,
606 IFXARB2_XTD | IFXARB2_MVAL | IFXARB2_DIR |
607 ((u16) (pmsg->id >> 16) & 0x1FFF), CCIF2A2);
609 c_can_write_reg_w(pmsgobj->hostchip,
610 (IFXARB2_MVAL | IFXARB2_DIR |
611 ((u16) (pmsg->id << 2) & 0x1FFC)), CCIF2A2);
612 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
615 if (pmsg->length > 0) {
616 dataA1 = pmsg->data[0] | (u16) pmsg->data[1] << 8;
617 dataA2 = pmsg->data[2] | (u16) pmsg->data[3] << 8;
618 dataB1 = pmsg->data[4] | (u16) pmsg->data[5] << 8;
619 dataB2 = pmsg->data[6] | (u16) pmsg->data[7] << 8;
621 c_can_write_reg_w(pmsgobj->hostchip, dataA1, CCIF2DA1);
622 c_can_write_reg_w(pmsgobj->hostchip, dataA2, CCIF2DA2);
623 c_can_write_reg_w(pmsgobj->hostchip, dataB1, CCIF2DB1);
624 c_can_write_reg_w(pmsgobj->hostchip, dataB2, CCIF2DB2);
627 c_can_write_reg_w(pmsgobj->hostchip, writeSendMskCM, CCIF2CM);
628 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
630 spin_unlock(&c_can_if2lock);
634 c_can_registerdump(pmsgobj->hostchip);
640 //////////////////////////////////////////////////////////////////////
641 int c_can_remote_request(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
643 unsigned short readMaskCM = IFXCM_CNTRL; // | IFXCM_ARB;
644 //unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
645 unsigned short mcreg = 0;
647 DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n",
648 pmsgobj->hostchip->chip_idx, pmsgobj->object);
650 //Remote request is only available when the message object is in receiving mode
651 if (!can_msgobj_test_fl(pmsgobj, RX_MODE)) {
655 spin_lock(&c_can_if1lock);
657 //loading Message Object in IF1
658 if (c_can_if1_busycheck(pmsgobj->hostchip))
660 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
661 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
662 //setting Transmit-Request-Bit
663 if (c_can_if1_busycheck(pmsgobj->hostchip))
665 mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
666 c_can_write_reg_w(pmsgobj->hostchip, mcreg | IFXMC_TXRQST, CCIF1DMC);
668 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
670 spin_unlock(&c_can_if1lock);
672 DEBUGMSG("-> Sent remote request through message object %d\n",
675 c_can_registerdump(pmsgobj->hostchip);
681 ///////////////////////////////////////////////////////////////////////
682 int c_can_set_btregs(struct canchip_t *pchip, u16 btr0, u16 btr1)
684 unsigned short tempCR = 0;
686 DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_idx);
692 if (c_can_enable_configuration(pchip))
695 //read Control Register
696 tempCR = c_can_read_reg_w(pchip, CCCR);
697 //Configuration Change Enable
698 c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
699 c_can_write_reg_w(pchip, btr0 | (btr1 << 8), CCBT);
701 if (c_can_disable_configuration(pchip))
708 ///////////////////////////////////////////////////////////////////////
710 * Starts the Chip, by setting the CAN Enable Bit
712 int c_can_start_chip(struct canchip_t *pchip)
716 DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_idx);
720 DEBUGMSG("-> Error Chip not available.\n");
723 #ifdef C_CAN_WITH_CCCE
724 flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
725 c_can_write_reg_w(pchip, flags, CCCE);
730 c_can_registerdump(pchip);
736 ///////////////////////////////////////////////////////////////////////
738 * Stops the Chip, by deleting the CAN Enable Bit
740 int c_can_stop_chip(struct canchip_t *pchip)
744 DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_idx);
748 DEBUGMSG("-> Error Chip not available.\n");
751 #ifdef C_CAN_WITH_CCCE
752 flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
753 c_can_write_reg_w(pchip, flags, CCCE);
760 int c_can_attach_to_chip(struct canchip_t *chip)
765 int c_can_release_chip(struct canchip_t *chip)
769 temp = c_can_read_reg_w(chip, CCCR);
771 /* Disable IRQ generation */
772 c_can_config_irqs(chip, 0);
774 temp = c_can_read_reg_w(chip, CCCR);
776 /* Power-down C_CAN, except this does nothing in the version 1.2 */
777 c_can_stop_chip(chip);
782 ///////////////////////////////////////////////////////////////////////
784 *Check the TxOK bit of the Status Register and resets it afterwards.
786 int c_can_check_tx_stat(struct canchip_t *pchip)
788 unsigned long tempstat = 0;
790 DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_idx);
796 tempstat = c_can_read_reg_w(pchip, CCSR);
798 if (tempstat & SR_TXOK) {
799 c_can_write_reg_w(pchip, tempstat & ~SR_TXOK, CCSR);
806 ///////////////////////////////////////////////////////////////////////
807 int c_can_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
809 can_preempt_disable();
811 can_msgobj_set_fl(obj, TX_REQUEST);
813 /* calls c_can_irq_write_handler synchronized with other invocations
814 from kernel and IRQ context */
815 c_can_irq_sync_activities(chip, obj);
817 can_preempt_enable();
821 ///////////////////////////////////////////////////////////////////////
822 int c_can_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
824 can_preempt_disable();
826 can_msgobj_set_fl(obj, FILTCH_REQUEST);
828 /* setups filter synchronized with other invocations from kernel and IRQ context */
829 c_can_irq_sync_activities(chip, obj);
831 can_preempt_enable();
835 ///////////////////////////////////////////////////////////////////////
836 void c_can_registerdump(struct canchip_t *pchip)
838 CANMSG("------------------------------------\n");
839 CANMSG("---------C-CAN Register Dump--------\n");
840 CANMSG("------------at 0x%.8lx-----------\n",
841 (unsigned long)pchip->chip_base_addr);
842 CANMSG("Control Register: 0x%.4lx\n",
843 (long)(c_can_read_reg_w(pchip, CCCR)));
844 CANMSG("Status Register: 0x%.4lx\n",
845 (long)(c_can_read_reg_w(pchip, CCSR)));
846 CANMSG("Error Counting Register: 0x%.4lx\n",
847 (long)(c_can_read_reg_w(pchip, CCEC)));
848 CANMSG("Bit Timing Register: 0x%.4lx\n",
849 (long)(c_can_read_reg_w(pchip, CCBT)));
850 CANMSG("Interrupt Register: 0x%.4lx\n",
851 (long)(c_can_read_reg_w(pchip, CCINTR)));
852 CANMSG("Test Register: 0x%.4lx\n",
853 (long)(c_can_read_reg_w(pchip, CCTR)));
854 CANMSG("Baud Rate Presc. Register: 0x%.4lx\n",
855 (long)(c_can_read_reg_w(pchip, CCBRPE)));
856 #ifdef C_CAN_WITH_CCCE
857 CANMSG("CAN Enable Register: 0x%.4lx\n",
858 (long)(c_can_read_reg_w(pchip, CCCE)));
860 CANMSG("Transm. Req. 1 Register: 0x%.4lx\n",
861 (long)(c_can_read_reg_w(pchip, CCTREQ1)));
862 CANMSG("Transm. Req. 2 Register: 0x%.4lx\n",
863 (long)(c_can_read_reg_w(pchip, CCTREQ2)));
864 CANMSG("New Data 1 Register: 0x%.4lx\n",
865 (long)(c_can_read_reg_w(pchip, CCND1)));
866 CANMSG("New Data 2 Register: 0x%.4lx\n",
867 (long)(c_can_read_reg_w(pchip, CCND2)));
868 CANMSG("Interrupt Pend. 1 Register: 0x%.4lx\n",
869 (long)(c_can_read_reg_w(pchip, CCINTP1)));
870 CANMSG("Interrupt Pend. 2 Register: 0x%.4lx\n",
871 (long)(c_can_read_reg_w(pchip, CCINTP2)));
872 CANMSG("------------------------------------\n");
873 CANMSG("IF1 Command Req. Register: 0x%.4lx\n",
874 (long)(c_can_read_reg_w(pchip, CCIF1CR)));
875 CANMSG("IF1 Command Mask Register: 0x%.4lx\n",
876 (long)(c_can_read_reg_w(pchip, CCIF1CM)));
877 CANMSG("IF1 Mask 1 Register: 0x%.4lx\n",
878 (long)(c_can_read_reg_w(pchip, CCIF1M1)));
879 CANMSG("IF1 Mask 2 Register: 0x%.4lx\n",
880 (long)(c_can_read_reg_w(pchip, CCIF1M2)));
881 CANMSG("IF1 Arbitration 1 Register: 0x%.4lx\n",
882 (long)(c_can_read_reg_w(pchip, CCIF1A1)));
883 CANMSG("IF1 Arbitration 2 Register: 0x%.4lx\n",
884 (long)(c_can_read_reg_w(pchip, CCIF1A2)));
885 CANMSG("IF1 Message Control Register: 0x%.4lx\n",
886 (long)(c_can_read_reg_w(pchip, CCIF1DMC)));
887 CANMSG("IF1 Data A1 Register: 0x%.4lx\n",
888 (long)(c_can_read_reg_w(pchip, CCIF1DA1)));
889 CANMSG("IF1 Data A2 Register: 0x%.4lx\n",
890 (long)(c_can_read_reg_w(pchip, CCIF1DA2)));
891 CANMSG("IF1 Data B1 Register: 0x%.4lx\n",
892 (long)(c_can_read_reg_w(pchip, CCIF1DB1)));
893 CANMSG("IF1 Data B2 Register: 0x%.4lx\n",
894 (long)(c_can_read_reg_w(pchip, CCIF1DB2)));
895 CANMSG("------------------------------------\n");
896 CANMSG("IF2 Command Req. Register: 0x%.4lx\n",
897 (long)(c_can_read_reg_w(pchip, CCIF2CR)));
898 CANMSG("IF2 Command Mask Register: 0x%.4lx\n",
899 (long)(c_can_read_reg_w(pchip, CCIF2CM)));
900 CANMSG("IF2 Mask 1 Register: 0x%.4lx\n",
901 (long)(c_can_read_reg_w(pchip, CCIF2M1)));
902 CANMSG("IF2 Mask 2 Register: 0x%.4lx\n",
903 (long)(c_can_read_reg_w(pchip, CCIF2M2)));
904 CANMSG("IF2 Arbitration 1 Register: 0x%.4lx\n",
905 (long)(c_can_read_reg_w(pchip, CCIF2A1)));
906 CANMSG("IF2 Arbitration 2 Register: 0x%.4lx\n",
907 (long)(c_can_read_reg_w(pchip, CCIF2A2)));
908 CANMSG("IF2 Message Control Register: 0x%.4lx\n",
909 (long)(c_can_read_reg_w(pchip, CCIF2DMC)));
910 CANMSG("IF2 Data A1 Register: 0x%.4lx\n",
911 (long)(c_can_read_reg_w(pchip, CCIF2DA1)));
912 CANMSG("IF2 Data A2 Register: 0x%.4lx\n",
913 (long)(c_can_read_reg_w(pchip, CCIF2DA2)));
914 CANMSG("IF2 Data B1 Register: 0x%.4lx\n",
915 (long)(c_can_read_reg_w(pchip, CCIF2DB1)));
916 CANMSG("IF2 Data B2 Register: 0x%.4lx\n",
917 (long)(c_can_read_reg_w(pchip, CCIF2DB2)));
918 CANMSG("------------------------------------\n");
919 CANMSG("------------------------------------\n");
922 void c_can_if1_registerdump(struct canchip_t *pchip)
924 CANMSG("----------------------------------------\n");
925 CANMSG("Error Counting Register: 0x%.4lx\n",
926 (long)(c_can_read_reg_w(pchip, CCEC)));
927 CANMSG("---------C-CAN IF1 Register Dump--------\n");
928 CANMSG("IF1 Command Req. Register: 0x%.4lx\n",
929 (long)(c_can_read_reg_w(pchip, CCIF1CR)));
930 CANMSG("IF1 Command Mask Register: 0x%.4lx\n",
931 (long)(c_can_read_reg_w(pchip, CCIF1CM)));
932 CANMSG("IF1 Mask 1 Register: 0x%.4lx\n",
933 (long)(c_can_read_reg_w(pchip, CCIF1M1)));
934 CANMSG("IF1 Mask 2 Register: 0x%.4lx\n",
935 (long)(c_can_read_reg_w(pchip, CCIF1M2)));
936 CANMSG("IF1 Arbitration 1 Register: 0x%.4lx\n",
937 (long)(c_can_read_reg_w(pchip, CCIF1A1)));
938 CANMSG("IF1 Arbitration 2 Register: 0x%.4lx\n",
939 (long)(c_can_read_reg_w(pchip, CCIF1A2)));
940 CANMSG("IF1 Message Control Register: 0x%.4lx\n",
941 (long)(c_can_read_reg_w(pchip, CCIF1DMC)));
942 CANMSG("IF1 Data A1 Register: 0x%.4lx\n",
943 (long)(c_can_read_reg_w(pchip, CCIF1DA1)));
944 CANMSG("IF1 Data A2 Register: 0x%.4lx\n",
945 (long)(c_can_read_reg_w(pchip, CCIF1DA2)));
946 CANMSG("IF1 Data B1 Register: 0x%.4lx\n",
947 (long)(c_can_read_reg_w(pchip, CCIF1DB1)));
948 CANMSG("IF1 Data B2 Register: 0x%.4lx\n",
949 (long)(c_can_read_reg_w(pchip, CCIF1DB2)));
952 ///////////////////////////////////////////////////////////////////////
954 int c_can_register(struct chipspecops_t *chipspecops)
956 CANMSG("initializing c_can chip operations\n");
957 chipspecops->chip_config = c_can_chip_config;
958 chipspecops->baud_rate = c_can_baud_rate;
959 /*chipspecops->standard_mask=c_can_standard_mask;
960 chipspecops->extended_mask=c_can_extended_mask;
961 chipspecops->message15_mask=c_can_extended_mask; */
962 chipspecops->clear_objects = c_can_clear_objects;
963 /*chipspecops->config_irqs=c_can_config_irqs; */
964 chipspecops->pre_read_config = c_can_pre_read_config;
965 chipspecops->pre_write_config = c_can_pre_write_config;
966 chipspecops->send_msg = c_can_send_msg;
967 chipspecops->check_tx_stat = c_can_check_tx_stat;
968 chipspecops->wakeup_tx = c_can_wakeup_tx;
969 chipspecops->filtch_rq = c_can_filtch_rq;
970 chipspecops->remote_request = c_can_remote_request;
971 chipspecops->enable_configuration = c_can_enable_configuration;
972 chipspecops->disable_configuration = c_can_disable_configuration;
973 chipspecops->attach_to_chip = c_can_attach_to_chip;
974 chipspecops->release_chip = c_can_release_chip;
975 chipspecops->set_btregs = c_can_set_btregs;
976 chipspecops->start_chip = c_can_start_chip;
977 chipspecops->stop_chip = c_can_stop_chip;
978 chipspecops->irq_handler = c_can_irq_handler;
979 chipspecops->irq_accept = NULL;
983 int c_can_fill_chipspecops(struct canchip_t *chip)
985 chip->chip_type = "c_can";
986 if (MAX_MSGOBJS >= 32) {
987 chip->max_objects = 32;
989 CANMSG("C_CAN requires 32 message objects per chip,"
990 " but only %d is compiled maximum\n", MAX_MSGOBJS);
991 chip->max_objects = MAX_MSGOBJS;
993 c_can_register(chip->chipspecops);