1 /* c_can.c - Hynix HMS30c7202 ARM generic C_CAN module handling
2 * Linux CAN-bus device driver.
3 * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de
4 * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl
5 * and Ake Hedman, eurosource, akhe@eurosource.se
6 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
7 * email:pisa@cmp.felk.cvut.cz
8 * This software is released under the GPL-License.
9 * Version lincan-0.2 9 Jul 2003
12 #define __NO_VERSION__
14 #include "../include/can.h"
15 #include "../include/can_sysdep.h"
16 #include "../include/main.h"
17 #include "../include/c_can.h"
22 can_spinlock_t c_can_spwlock=SPIN_LOCK_UNLOCKED; // Spin lock for write operations
23 can_spinlock_t c_can_sprlock=SPIN_LOCK_UNLOCKED; // Spin lock for read operations
24 can_spinlock_t c_can_if1lock=SPIN_LOCK_UNLOCKED; // spin lock for the if1 register
25 can_spinlock_t c_can_if2lock=SPIN_LOCK_UNLOCKED; // spin lcok for the if2 register
28 * c_can_enable_configuration - enable chip configuration mode
29 * @pchip: pointer to chip state structure
31 int c_can_enable_configuration(struct chip_t *pchip)
35 DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n", pchip->chip_nr);
37 DEBUGMSG("Trying disable_irq(...) : ");
39 disable_irq(chip->chip_irq);
41 //read Control Register
42 flags=c_can_read_reg_w(pchip, CCCR);
43 //set Init-Bit in the Control Register (10 tries)
44 while ((!(flags & CR_INIT)) && (i<=10))
46 c_can_write_reg_w(pchip,flags|CR_INIT, CCCR);
49 flags=c_can_read_reg_w(pchip, CCCR);
53 CANMSG("Reset error\n");
54 //enable_irq(chip->chip_irq);
62 ///////////////////////////////////////////////////////////////////////
63 int c_can_disable_configuration(struct chip_t *pchip)
68 DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n", pchip->chip_nr);
69 //read Control Register
70 flags=c_can_read_reg_w(pchip, CCCR);
72 //reset Init-Bit in the Control Register (10 tries)
73 while ( (flags & CR_INIT) && (i<=10) )
75 c_can_write_reg_w( pchip,flags & ~CR_INIT, CCCR);
76 udelay(1000); //100 microseconds
78 flags=c_can_read_reg_w(pchip, CCCR);
82 CANMSG("Error leaving reset status\n");
87 //enable_irq(chip->chip_irq);
92 ///////////////////////////////////////////////////////////////////////
93 int c_can_chip_config(struct chip_t *pchip)
96 DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_nr);
98 if ( NULL == pchip ) return -1;
100 if (pchip->baudrate == 0)
101 pchip->baudrate=1000;
103 if (c_can_baud_rate(pchip,pchip->baudrate*1000,pchip->clock,0,75,0))
105 CANMSG("Error configuring baud rate\n");
109 if (c_can_extended_mask(pchip,0x0000000,extmask)) {
110 CANMSG("Error configuring extended mask\n");
114 if (c_can_standard_mask(pchip,0x0000,stdmask)) {
115 CANMSG("Error configuring standard mask\n");
119 if (c_can_clear_objects(pchip))
121 CANMSG("Error clearing message objects\n");
124 if (c_can_config_irqs(pchip, CR_MIE | CR_SIE | CR_EIE))
126 CANMSG("Error configuring interrupts\n");
130 DEBUGMSG("-> Configured successfully\n");
133 c_can_registerdump(pchip);
139 ///////////////////////////////////////////////////////////////////////
141 * Checks if the Busy-Bit in the IF1-Command-Request Register is set
143 int c_can_if1_busycheck(struct chip_t *pchip)
147 unsigned short comreg = 0;
149 comreg = c_can_read_reg_w( pchip, CCIF1CR);
150 while ( (comreg & IFXCR_BUSY) && (i<=10) )
152 udelay(100); //100 microseconds
154 comreg=c_can_read_reg_w( pchip, CCIF1CR);
158 CANMSG("Error Busy-Bit stays set\n");
165 ///////////////////////////////////////////////////////////////////////
167 * Checks if the Busy-Bit in the IF2-Command-Request Register is set
169 int c_can_if2_busycheck(struct chip_t *pchip)
173 unsigned short comreg = 0;
175 comreg = c_can_read_reg_w( pchip, CCIF2CR);
176 while ( (comreg & IFXCR_BUSY) && (i<=10) )
178 udelay(100); //100 microseconds
180 comreg=c_can_read_reg_w( pchip, CCIF2CR);
184 CANMSG("Error Busy-Bit stays set\n");
191 ///////////////////////////////////////////////////////////////////////
193 * Though the C-CAN Chip can handle one mask for each Message Object, this Method defines
194 * one mask for all MOs. That means every MO gets the same mask.
197 /* Set communication parameters.
198 * param rate baud rate in Hz
199 * param clock frequency of C-CAN clock in Hz
200 * param sjw synchronization jump width (0-3) prescaled clock cycles
201 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
202 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
204 int c_can_baud_rate(struct chip_t *pchip, int rate, int clock,
205 int sjw, int sampl_pt, int flags)
207 int best_error = 1000000000, error;
208 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
209 int tseg=0, tseg1=0, tseg2=0;
211 unsigned short tempCR = 0;
213 DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_nr);
215 if (c_can_enable_configuration(pchip))
220 /* tseg even = round down, odd = round up */
221 for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++)
223 brp = clock/((1+tseg/2)*rate)+tseg%2;
224 if (brp == 0 || brp > 64)
226 error = rate - clock/(brp*(1+tseg/2));
229 if (error <= best_error)
234 best_rate = clock/(brp*(1+tseg/2));
237 if (best_error && (rate/best_error < 10))
239 CANMSG("baud rate %d is not possible with %d Hz clock\n",
241 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
242 best_rate, best_brp, best_tseg, tseg1, tseg2);
245 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
248 if (tseg2 > MAX_TSEG2)
250 tseg1 = best_tseg-tseg2-2;
251 if (tseg1 > MAX_TSEG1)
254 tseg2 = best_tseg-tseg1-2;
257 DEBUGMSG("-> Setting %d bps.\n", best_rate);
258 DEBUGMSG("->brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
259 best_brp, best_tseg, tseg1, tseg2,
260 (100*(best_tseg-tseg2)/(best_tseg+1)));
262 //read Control Register
263 tempCR = c_can_read_reg_w( pchip, CCCR);
264 //Configuration Change Enable
265 c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
266 c_can_write_reg_w(pchip, ((unsigned short)tseg2)<<12 | ((unsigned short)tseg1)<<8
267 | (unsigned short)sjw<<6 | (unsigned short) best_brp,
270 if (c_can_disable_configuration(pchip))
276 ///////////////////////////////////////////////////////////////////////
277 int c_can_mask(struct msgobj_t *pmsgobj,
281 unsigned short tempreg = 0;
282 unsigned short readMaskCM;
283 unsigned short writeMaskCM;
285 DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
287 readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK;
288 writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK | IFXCM_WRRD;
290 spin_lock( &c_can_if1lock );
292 //load Message Object in IF1
293 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
294 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
295 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
297 //setting Message Valid Bit to zero
298 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
299 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
300 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~(IFXARB2_MVAL), CCIF1A2);
301 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
302 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
304 //setting UMask, MsgVal and Mask Register
305 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
307 //writing acceptance mask for extended or standart mode
308 if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
311 c_can_write_reg_w(pmsgobj->hostchip,
312 (mask>>16 & 0x1FFF) | IFXMSK2_MXTD | IFXMSK2_MDIR, CCIF1M2);
314 c_can_write_reg_w(pmsgobj->hostchip,
315 (mask>>16 & 0x1FFF) | IFXMSK2_MXTD, CCIF1M2);
316 c_can_write_reg_w(pmsgobj->hostchip, (mask & 0xFFFF), CCIF1M1);
321 c_can_write_reg_w(pmsgobj->hostchip,
322 ((mask<<2) & 0x1FFC) | IFXMSK2_MDIR, CCIF1M2);
324 c_can_write_reg_w(pmsgobj->hostchip,
325 ((mask<<2) & 0x1FFC), CCIF1M2);
326 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
328 //seting Message Valid Bit to one
329 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
330 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
332 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
333 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
335 spin_unlock( &c_can_if1lock );
337 DEBUGMSG("-> Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
340 c_can_registerdump(pmsgobj->hostchip);
346 ///////////////////////////////////////////////////////////////////////
347 int c_can_use_mask(struct msgobj_t *pmsgobj,
350 unsigned short tempreg = 0;
351 unsigned short readMaskCM;
352 unsigned short writeMaskCM;
355 char *boolstring = "false";
356 if (useflag) boolstring = "true";
358 DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
360 readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
361 writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;
363 spin_lock( &c_can_if1lock );
365 //load Message Object in IF1
366 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
367 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
368 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
370 //setting Message Valid Bit to zero
371 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
372 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
373 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
374 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
375 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
378 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
381 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
382 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK, CCIF1DMC);
386 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
387 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXMC_UMASK, CCIF1DMC);
389 //seting Message Valid Bit to one
390 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
391 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
393 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
394 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
396 spin_unlock( &c_can_if1lock );
399 DEBUGMSG("-> Setting umask bit to %s\n",boolstring);
402 c_can_registerdump(pmsgobj->hostchip);
408 ///////////////////////////////////////////////////////////////////////
409 int c_can_clear_objects(struct chip_t *pchip)
411 unsigned short i = 0;
412 unsigned short tempreg = 0;
414 unsigned short maskCM = IFXCM_ARB;
416 DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_nr);
418 spin_lock( &c_can_if1lock );
419 spin_lock( &c_can_if2lock );
421 for (i=0; i<0x10; i++)
424 //loading Message Objects in IF1 and IF2
425 if (c_can_if1_busycheck(pchip)) return -ENODEV;
426 c_can_write_reg_w(pchip, maskCM, CCIF1CM);
427 c_can_write_reg_w(pchip, i, CCIF1CR);
428 if (c_can_if2_busycheck(pchip)) return -ENODEV;
429 c_can_write_reg_w(pchip, maskCM, CCIF2CM);
430 c_can_write_reg_w(pchip, i+0x10, CCIF2CR);
432 //setting Message Valid Bit to zero
433 if (c_can_if1_busycheck(pchip)) return -ENODEV;
434 tempreg = c_can_read_reg_w(pchip, CCIF1A2);
435 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
436 c_can_write_reg_w(pchip, i, CCIF1CR);
437 if (c_can_if2_busycheck(pchip)) return -ENODEV;
438 tempreg = c_can_read_reg_w(pchip, CCIF2A2);
439 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF2A2);
440 c_can_write_reg_w(pchip, i+0x10, CCIF2CR);
443 for (i=0; i<pchip->max_objects; i++)
445 if (can_msgobj_test_fl(pchip->msgobj[i],OPENED))
447 // In- and output buffer re-initialization
448 canqueue_ends_flush_inlist(pchip->msgobj[i]->qends);
449 canqueue_ends_flush_outlist(pchip->msgobj[i]->qends);
454 spin_unlock( &c_can_if1lock );
455 spin_unlock( &c_can_if2lock );
457 DEBUGMSG("-> Message Objects reset\n");
462 ///////////////////////////////////////////////////////////////////////
463 int c_can_config_irqs(struct chip_t *pchip,
468 DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_nr);
471 CANMSG("c_can_config_irqs not implemented\n");
475 tempreg = c_can_read_reg_w(pchip, CCCR);
476 //DEBUGMSG("-> CAN Control Register: 0x%.4lx\n",(long)tempreg);
477 c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
478 DEBUGMSG("-> Configured hardware interrupt delivery\n");
482 ///////////////////////////////////////////////////////////////////////
483 int c_can_pre_read_config(struct chip_t *pchip, struct msgobj_t *pmsgobj)
485 unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
486 unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
487 unsigned short mcreg = 0;
488 u32 id=pmsgobj->rx_preconfig_id;
490 DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
492 spin_lock( &c_can_if1lock );
495 //loading Message Object in IF1
496 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
497 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
498 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
499 //setting Message Valid Bit to zero
500 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
501 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A2);
502 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
503 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
504 //Configuring Message-Object
505 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
506 mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1CM);
507 c_can_write_reg_w(pmsgobj->hostchip,
508 ((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE), CCIF1DMC);
509 //writing arbitration mask for extended or standart mode
510 if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
512 c_can_write_reg_w(pmsgobj->hostchip,
513 IFXARB2_XTD | IFXARB2_MVAL | (id>>16 & 0x1FFF), CCIF1A2);
514 c_can_write_reg_w(pmsgobj->hostchip, id & 0xFFFF, CCIF1A1);
518 c_can_write_reg_w(pmsgobj->hostchip,
519 IFXARB2_MVAL | (id<<2 & 0x1FFC), CCIF1A2);
520 //c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
522 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
523 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
525 spin_unlock( &c_can_if1lock );
527 DEBUGMSG("-> Receiving through message object %d with id=%d\n", pmsgobj->object,
530 c_can_registerdump(pmsgobj->hostchip);
536 ///////////////////////////////////////////////////////////////////////
537 int c_can_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
538 struct canmsg_t *msg)
543 ///////////////////////////////////////////////////////////////////////
545 *Prepare the Chip to send specified Message over specified Messageobject
546 *In this version the method also sends the message.
549 int c_can_send_msg(struct chip_t *pchip, struct msgobj_t *pmsgobj,
550 struct canmsg_t *pmsg)
552 unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB;
553 unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD;
554 unsigned short writeSendMskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD | IFXCM_TRND;
555 unsigned short mcreg = 0;
556 //unsigned short arbreg = 0;
557 unsigned short dataA1 = 0;
558 unsigned short dataA2 = 0;
559 unsigned short dataB1 = 0;
560 unsigned short dataB2 = 0;
562 DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
564 spin_lock( &c_can_if2lock );
566 can_msgobj_clear_fl(pmsgobj,RX_MODE);
568 //loading Message Object in IF1
569 if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
570 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF2CM);
571 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
572 //setting Message Valid Bit to zero
573 if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
574 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF2A2);
575 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF2CM);
576 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
578 if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
579 mcreg = c_can_read_reg_w( pmsgobj->hostchip, CCIF2CM);
581 //define Command Mask
582 c_can_write_reg_w(pmsgobj->hostchip, (mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_TXIE
583 | IFXMC_RMTEN | IFXMC_NEWDAT | IFXMC_TXRQST | (pmsg->length & 0xF), CCIF2DMC);
584 //set Arbitration Bits
585 if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
587 c_can_write_reg_w(pmsgobj->hostchip, (u16)(pmsg->id), CCIF2A1);
588 c_can_write_reg_w(pmsgobj->hostchip, IFXARB2_XTD | IFXARB2_MVAL | IFXARB2_DIR
589 | ((u16)(pmsg->id>>16) & 0x1FFF), CCIF2A2);
593 c_can_write_reg_w(pmsgobj->hostchip,
594 (IFXARB2_MVAL | IFXARB2_DIR | ((u16)(pmsg->id<<2) & 0x1FFC)), CCIF2A2);
595 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
600 dataA1 = pmsg->data[0] | (u16)pmsg->data[1]<<8;
601 dataA2 = pmsg->data[2] | (u16)pmsg->data[3]<<8;
602 dataB1 = pmsg->data[4] | (u16)pmsg->data[5]<<8;
603 dataB2 = pmsg->data[6] | (u16)pmsg->data[7]<<8;
605 c_can_write_reg_w(pmsgobj->hostchip, dataA1, CCIF2DA1);
606 c_can_write_reg_w(pmsgobj->hostchip, dataA2, CCIF2DA2);
607 c_can_write_reg_w(pmsgobj->hostchip, dataB1, CCIF2DB1);
608 c_can_write_reg_w(pmsgobj->hostchip, dataB2, CCIF2DB2);
611 c_can_write_reg_w(pmsgobj->hostchip, writeSendMskCM, CCIF2CM);
612 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
614 spin_unlock( &c_can_if2lock );
618 c_can_registerdump(pmsgobj->hostchip);
624 //////////////////////////////////////////////////////////////////////
625 int c_can_remote_request(struct chip_t *pchip, struct msgobj_t *pmsgobj )
627 unsigned short readMaskCM = IFXCM_CNTRL;// | IFXCM_ARB;
628 //unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
629 unsigned short mcreg = 0;
631 DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
633 //Remote request is only available when the message object is in receiving mode
634 if (!can_msgobj_test_fl(pmsgobj,RX_MODE))
639 spin_lock( &c_can_if1lock );
641 //loading Message Object in IF1
642 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
643 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
644 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
645 //setting Transmit-Request-Bit
646 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
647 mcreg = c_can_read_reg_w( pmsgobj->hostchip, CCIF1DMC);
648 c_can_write_reg_w(pmsgobj->hostchip, mcreg | IFXMC_TXRQST, CCIF1DMC);
650 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
652 spin_unlock( &c_can_if1lock );
654 DEBUGMSG("-> Sent remote request through message object %d\n", pmsgobj->object);
656 c_can_registerdump(pmsgobj->hostchip);
662 ///////////////////////////////////////////////////////////////////////
663 int c_can_set_btregs(struct chip_t *pchip,
667 unsigned short tempCR = 0;
669 DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_nr);
672 if ( NULL == pchip ) return -1;
674 if (c_can_enable_configuration(pchip))
677 //read Control Register
678 tempCR = c_can_read_reg_w(pchip, CCCR);
679 //Configuration Change Enable
680 c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
681 c_can_write_reg_w(pchip, btr0 | (btr1<<8), CCBT);
683 if (c_can_disable_configuration(pchip))
690 ///////////////////////////////////////////////////////////////////////
692 * Starts the Chip, by setting the CAN Enable Bit
694 int c_can_start_chip(struct chip_t *pchip)
698 DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_nr);
703 DEBUGMSG("-> Error Chip not available.\n");
707 // flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
708 // c_can_write_reg_w(pchip, flags, CCCE);
710 flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
711 c_can_write_reg_w(pchip, flags, CCCE);
715 c_can_registerdump(pchip);
721 ///////////////////////////////////////////////////////////////////////
723 * Stops the Chip, by deleting the CAN Enable Bit
725 int c_can_stop_chip(struct chip_t *pchip)
729 DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_nr);
734 DEBUGMSG("-> Error Chip not available.\n");
738 flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
739 c_can_write_reg_w(pchip, flags, CCCE);
745 ///////////////////////////////////////////////////////////////////////
747 *Check the TxOK bit of the Status Register and resets it afterwards.
749 int c_can_check_tx_stat(struct chip_t *pchip)
751 unsigned long tempstat = 0;
753 DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_nr);
756 if ( NULL == pchip ) return -1;
758 tempstat = c_can_read_reg_w(pchip, CCSR);
760 if (tempstat & SR_TXOK)
762 c_can_write_reg_w(pchip, tempstat & ~SR_TXOK, CCSR);
772 ///////////////////////////////////////////////////////////////////////
773 int c_can_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
775 can_preempt_disable();
777 can_msgobj_set_fl(obj,TX_REQUEST);
779 /* calls i82527_irq_write_handler synchronized with other invocations
780 from kernel and IRQ context */
781 c_can_irq_sync_activities(chip, obj);
783 can_preempt_enable();
787 ///////////////////////////////////////////////////////////////////////
788 int c_can_filtch_rq(struct chip_t *chip, struct msgobj_t *obj)
790 can_preempt_disable();
792 can_msgobj_set_fl(obj,FILTCH_REQUEST);
794 /* setups filter synchronized with other invocations from kernel and IRQ context */
795 c_can_irq_sync_activities(chip, obj);
797 can_preempt_enable();
802 ///////////////////////////////////////////////////////////////////////
803 void c_can_registerdump(struct chip_t *pchip)
805 CANMSG("------------------------------------\n");
806 CANMSG("---------C-CAN Register Dump--------\n");
807 CANMSG("------------at 0x%.8lx-----------\n"
808 ,(unsigned long)pchip->chip_base_addr);
809 CANMSG("Control Register: 0x%.4lx\n",
810 (long)(c_can_read_reg_w( pchip, CCCR)));
811 CANMSG("Status Register: 0x%.4lx\n",
812 (long)(c_can_read_reg_w( pchip, CCSR)));
813 CANMSG("Error Counting Register: 0x%.4lx\n",
814 (long)(c_can_read_reg_w( pchip, CCEC)));
815 CANMSG("Bit Timing Register: 0x%.4lx\n",
816 (long)(c_can_read_reg_w( pchip, CCBT)));
817 CANMSG("Interrupt Register: 0x%.4lx\n",
818 (long)(c_can_read_reg_w( pchip, CCINTR)));
819 CANMSG("Test Register: 0x%.4lx\n",
820 (long)(c_can_read_reg_w( pchip, CCTR)));
821 CANMSG("Baud Rate Presc. Register: 0x%.4lx\n",
822 (long)(c_can_read_reg_w( pchip, CCBRPE)));
823 CANMSG("CAN Enable Register: 0x%.4lx\n",
824 (long)(c_can_read_reg_w( pchip, CCCE)));
825 CANMSG("Transm. Req. 1 Register: 0x%.4lx\n",
826 (long)(c_can_read_reg_w( pchip, CCTREQ1)));
827 CANMSG("Transm. Req. 2 Register: 0x%.4lx\n",
828 (long)(c_can_read_reg_w( pchip, CCTREQ2)));
829 CANMSG("New Data 1 Register: 0x%.4lx\n",
830 (long)(c_can_read_reg_w( pchip, CCND1)));
831 CANMSG("New Data 2 Register: 0x%.4lx\n",
832 (long)(c_can_read_reg_w( pchip, CCND2)));
833 CANMSG("Interrupt Pend. 1 Register: 0x%.4lx\n",
834 (long)(c_can_read_reg_w( pchip, CCINTP1)));
835 CANMSG("Interrupt Pend. 2 Register: 0x%.4lx\n",
836 (long)(c_can_read_reg_w( pchip, CCINTP2)));
837 CANMSG("------------------------------------\n");
838 CANMSG("IF1 Command Req. Register: 0x%.4lx\n",
839 (long)(c_can_read_reg_w( pchip, CCIF1CR)));
840 CANMSG("IF1 Command Mask Register: 0x%.4lx\n",
841 (long)(c_can_read_reg_w( pchip, CCIF1CM)));
842 CANMSG("IF1 Mask 1 Register: 0x%.4lx\n",
843 (long)(c_can_read_reg_w( pchip, CCIF1M1)));
844 CANMSG("IF1 Mask 2 Register: 0x%.4lx\n",
845 (long)(c_can_read_reg_w( pchip, CCIF1M2)));
846 CANMSG("IF1 Arbitration 1 Register: 0x%.4lx\n",
847 (long)(c_can_read_reg_w( pchip, CCIF1A1)));
848 CANMSG("IF1 Arbitration 2 Register: 0x%.4lx\n",
849 (long)(c_can_read_reg_w( pchip, CCIF1A2)));
850 CANMSG("IF1 Message Control Register: 0x%.4lx\n",
851 (long)(c_can_read_reg_w( pchip, CCIF1DMC)));
852 CANMSG("IF1 Data A1 Register: 0x%.4lx\n",
853 (long)(c_can_read_reg_w( pchip, CCIF1DA1)));
854 CANMSG("IF1 Data A2 Register: 0x%.4lx\n",
855 (long)(c_can_read_reg_w( pchip, CCIF1DA2)));
856 CANMSG("IF1 Data B1 Register: 0x%.4lx\n",
857 (long)(c_can_read_reg_w( pchip, CCIF1DB1)));
858 CANMSG("IF1 Data B2 Register: 0x%.4lx\n",
859 (long)(c_can_read_reg_w( pchip, CCIF1DB2)));
860 CANMSG("------------------------------------\n");
861 CANMSG("IF2 Command Req. Register: 0x%.4lx\n",
862 (long)(c_can_read_reg_w( pchip, CCIF2CR)));
863 CANMSG("IF2 Command Mask Register: 0x%.4lx\n",
864 (long)(c_can_read_reg_w( pchip, CCIF2CM)));
865 CANMSG("IF2 Mask 1 Register: 0x%.4lx\n",
866 (long)(c_can_read_reg_w( pchip, CCIF2M1)));
867 CANMSG("IF2 Mask 2 Register: 0x%.4lx\n",
868 (long)(c_can_read_reg_w( pchip, CCIF2M2)));
869 CANMSG("IF2 Arbitration 1 Register: 0x%.4lx\n",
870 (long)(c_can_read_reg_w( pchip, CCIF2A1)));
871 CANMSG("IF2 Arbitration 2 Register: 0x%.4lx\n",
872 (long)(c_can_read_reg_w( pchip, CCIF2A2)));
873 CANMSG("IF2 Message Control Register: 0x%.4lx\n",
874 (long)(c_can_read_reg_w( pchip, CCIF2DMC)));
875 CANMSG("IF2 Data A1 Register: 0x%.4lx\n",
876 (long)(c_can_read_reg_w( pchip, CCIF2DA1)));
877 CANMSG("IF2 Data A2 Register: 0x%.4lx\n",
878 (long)(c_can_read_reg_w( pchip, CCIF2DA2)));
879 CANMSG("IF2 Data B1 Register: 0x%.4lx\n",
880 (long)(c_can_read_reg_w( pchip, CCIF2DB1)));
881 CANMSG("IF2 Data B2 Register: 0x%.4lx\n",
882 (long)(c_can_read_reg_w( pchip, CCIF2DB2)));
883 CANMSG("------------------------------------\n");
884 CANMSG("------------------------------------\n");
887 ///////////////////////////////////////////////////////////////////////
889 int c_can_register(struct chipspecops_t *chipspecops)
891 CANMSG("initializing c_can chip operations\n");
892 chipspecops->chip_config=c_can_chip_config;
893 chipspecops->baud_rate=c_can_baud_rate;
894 /*chipspecops->standard_mask=c_can_standard_mask;
895 chipspecops->extended_mask=c_can_extended_mask;
896 chipspecops->message15_mask=c_can_extended_mask;*/
897 chipspecops->clear_objects=c_can_clear_objects;
898 /*chipspecops->config_irqs=c_can_config_irqs;*/
899 chipspecops->pre_read_config=c_can_pre_read_config;
900 chipspecops->pre_write_config=c_can_pre_write_config;
901 chipspecops->send_msg=c_can_send_msg;
902 chipspecops->check_tx_stat=c_can_check_tx_stat;
903 chipspecops->wakeup_tx=c_can_wakeup_tx;
904 chipspecops->filtch_rq = c_can_filtch_rq;
905 chipspecops->remote_request=c_can_remote_request;
906 chipspecops->enable_configuration=c_can_enable_configuration;
907 chipspecops->disable_configuration=c_can_disable_configuration;
908 chipspecops->set_btregs=c_can_set_btregs;
909 chipspecops->start_chip=c_can_start_chip;
910 chipspecops->stop_chip=c_can_stop_chip;
911 chipspecops->irq_handler=c_can_irq_handler;
915 /*int c_can_register(struct chip_t *pchip)
917 DEBUGMSG("(c%d)call c_can_register\n", pchip->chip_nr);
920 if ( NULL == pchip ) return -1;
922 pchip->chip_config = c_can_chip_config;
923 pchip->set_baud_rate = c_can_baud_rate;
924 pchip->set_mask = c_can_mask;
925 pchip->set_use_mask = c_can_use_mask;
926 //pchip->set_message15_mask = c_can_extended_mask;
927 pchip->clear_objects = c_can_clear_objects;
928 pchip->config_irqs = c_can_config_irqs;
929 pchip->pre_read_config = c_can_pre_read_config;
930 //pchip->pre_write_config = c_can_pre_write_config;
931 pchip->send_msg = c_can_send_msg;
932 pchip->check_tx_stat = c_can_check_tx_stat;
933 pchip->remote_request = c_can_remote_request;
934 pchip->enable_configuration = c_can_enable_configuration;
935 pchip->disable_configuration = c_can_disable_configuration;
936 pchip->set_btregs = c_can_set_btregs;
937 pchip->start_chip = c_can_start_chip;
938 pchip->stop_chip = c_can_stop_chip;
939 pchip->register_dump = c_can_registerdump;